( SNUG 00 Item 12 ) -------------------------------------------- [ 4/05/00 ]
WE PLAY BOTH COUNTRY AND WESTERN MUSIC: To the great glee of the Synopsys
physical synthesis marketing droids, the backend place & route world is
still very much evenly split between Cadence and Avanti. (They just love
this because PhysOpt is the only physical synthesis tool that's compatible
in both the Cadence and Avanti backend flows.)
Avanti Apollo ########### 23%
Cadence Silicon Ensemble ########### 22%
Avanti Star Tools ###### 13%
Mentor xCalibre #### 8%
Avanti Milkyway Database ##### 11%
Avanti Taurus 1%
Cadence Dracula ########### 22%
Avanti Hercules #### 9%
Synopsys EPIC CoreMill 1%
Mentor's Calibre was missing from the SNUG'00 user survey, but it easily
owns the physical verification (i.e. tools that check GDSII plots for
errors) market. According to Dataquest's 1998 numbers, Mentor's Calibre
had 40 percent, Cadence Dracula 29 percent, & Avanti Hercules 28 percent
market share. EPIC CoreMill wasn't on the radar screen back in 1998, and
it still wasn't noticed now in 2000.
"So now we know we've got a cross-capacitance problem, and we know we
can't just blindly jam buffers in to fix it, so what do we do? We go
check out the signal integrity option on Cadence Silicon Ensemble.
The best thing I can say for SE is that it runs without crashing.
Here are the problems we've found:
1. The parasitics coming from HyperExtract are up to 200% off
compared to 3D field solution. A chimpanzee throwing darts
at a diagram of parasitics could do better.
2. It's flagging over 1000 noise violations in a few hundred K
gates of logic. Over 1K noise violations in < 9mm^^2 of
randomly routed die? Gimme a break! Simulation showed that
SE was over-estimating noise by > 100%. It was using a slew
rate less than half of the actual slew rate. Its hard to say
how many real noise violations are in there, but my simulations
are saying my usual layout topologies ought to give me < 10
noise violations per 100K gates *usually*. Not 1000!
3. The repair file isn't. I'm still playing around with this to see
if other PBopt options might get me a better repair rate, but so
far I'm still left with A LOT of xcap timing and noise violations
reported even after I run through the check/repair flow a couple
of times. Given that these results are based on the HyperExtract
parasitics that I know to be bogus, I'm not really motivated to
run this into the ground. To me, the whole solution has the feel
of something that isn't going to gel.
Lesson learned: Just because your EDA or ASIC vendor shows you a
pretty drawing of a flow, don't buy it until you see the parasitic,
noise, and delay modeling correlation. Cross-capacitance isn't like
bringing a router up where the right values for metal pitch go a long
ways towards getting you something reasonably DRC clean. Cross-cap and
noise really require some tuning before you get back something clean."
- [ Born To Run ] from ESNUG 348 #6
"Give me 2 million gates flat and one Avanti license. I'll give you
a fully laid-out design."
- overheard at SNUG'00 conference
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