( SNUG 00 Item 10 ) -------------------------------------------- [ 4/05/00 ]
"Here are the commands Synopsys stressed to create smaller designs:
set_max_area 0 - Since version 1998, area optimization is not carried
out unless this constraint is set.
hdlin_infer_mux = "all" - This allows mapping to MUXes. Synopsys
assumes that most cell libraries best tuned and area utilized
cell with the MUX.
hdlin_infer_multibit = "default_all" - This allow the use of library
cells that have multi-bit components (registers, MUXes...)
hlo_resource_allocation = area_only - Only use for designs that have
non-critical timing.
hlo_resource_implementation = area_only - used together with the above
transform_csa - will convert an add array (a+b+c+d+e...) to a
csa tree to reduce logic, and create a faster design.
set_simple_command_mode true - generate a faster compile, reduces area,
should not uniquify design. (Again, only used for timing
critical designs.)
compile -map_effort med -area_effort high - now the compile has an area
effort switch. Note, that if map_effort is high will
automatically set area_effort high.
compile_sequential_area_recovery = true - Remaps all sequential cells
to recover area.
set_dont_use {list of high drive cells} - only do this in the first
compile... Allows initial mapping to use lower-drive cells,
will reduce runtime by eliminating cell downsizing.
ungroup - removes hierarchy, and could possibly reduce size.
compile -boundary_optimization - optimize across boundaries.
compile_new_boolean_structure - enables new boolean structure.
set_structure true -boolean true - Must go with the
compile_new_boolean_structure. Reduce area of don't care
logic by using logic reduction techniques.
I liked this particular tutorial a lot. It was full of useful tips."
- an anon engineer
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