( SNUG 00 Item 6 ) --------------------------------------------- [ 4/05/00 ]

   "Frank Emnett's presentation on Power Reduction Through RTL Clock
    Gating with Power Compiler was the most impressive one I saw.  He
    achieved a 50 percent reduction in power without changing his RTL!
    I'm impressed and will now consider Power Compiler where I was never
    much interested before.  According to Synopsys, Formality supports
    equivalence checking with RTL clock gating as well."

        - an anon engineer
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   !!!     "It's not a BUG,
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