( SNUG 00 Item 4 ) --------------------------------------------- [ 4/05/00 ]
"All tools suck. Some just suck less than others."
- the motto of the unknown physical design engineer
The Bigwig's Big Speech
-----------------------
"The high points of Aart's speech is that Synopsys is going into the
physical space because with deep submicron, it is needed. They now
have an integrated floor-plan manager, top level router, and
placer/synthesis. He said that they would soon have a router this
year. He bragged about 6 designs that were taped out using PhysOpt,
but when John Cooley asked for the names of the companies, Aart just
said that they were from the same family as most of the ESNUG posting,
Anonymous! He showed slide that compared 1st pass timing from a chip
that was synthesized with Design Compiler, and placed/routed with Avanti
P&R to a chip that was synthesized with PhysOpt, and routed with Avanti.
The Design Compiler results had a few nets that were broken by -3.2 ns
(200 Mhz system clock), and quite a few (in the 100's) that were broken
by -2.3 ns. The PhysOpt results had just a few nets broke by -0.64ns,
and most meeting timing. Aart also mentioned that they are also adding
clock tree synthesis to their new physical tools. He also said that
the COSSAP tool will be replaced this year, and its custom input
language will be replaced with SystemC. He also strongly hinted at a
SystemC to RTL/gates synthesis engine."
- an anon engineer
"Why did Aart de Geus hype up verification as one of the 3 key problem
areas facing customers and yet not hardly even mention Vera? Vera is
the only tool in his arsenal that has any hope of making major
improvements in verification productivity. You may not agree, John,
as many engineers do not, but as someone who has used Vera I am quite
confident that it at least contains the seeds for significantly
advancing the state of verification today. I thought it was a glaring
omission. Should I buy stock in Verisity?"
- an anon engineer
"Where, oh, where did my sweet VERA go? In Aart's speech, VERA was last
year's big news. This time around, VERA hardly got a mention. Just a
little bubble on the side of one of his slides. Is VERA the 90 miles
per gallon carburetor that Synopsys bought but will put on the shelf?
Seems Art and Synopsys are going to push SystemC instead."
- Peet James of Qualis Design
"Most out-to-lunch quote? Aart's comment that we'll all be writing our
ASIC code in SystemC, so we better prepare ourselves professionally,
was pretty out-to-lunch. Didn't Aart tell us 4 years ago that we'd all
be writing Behavioral Compiler code by now?"
- an anon engineer
"Synopsys is once again trying to increase the level of abstraction in
product development from RTL to higher level languages. Aart's latest
attempt (after the failure of Behavioral Compiler to catch on) is
SystemC. Aart made an non-announcement announcement that Synopsys
would be offering a tool to synthesize SystemC into gates by the end
of the year."
- an anon engineer
|
|
