( SNUG 00 Item 2 ) --------------------------------------------- [ 4/05/00 ]
The Numbers
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Throughout this year's SNUG'00 Trip Report you'll be seeing all sorts of
statistics flying around. This data comes from the customer survey taken
at the SNUG'00 meeting itself. A total of 305 out of the 474 SNUG'00
attendees responded on this survey. Also, be very aware that all of these
stats have a +/- 6 percent margin of error. This means for every number
you see, the REAL TRUE percentage as projected to ALL SYNOPSYS CUSTOMERS
is within +/- 6 percent of the number you're seeing reported here.
So, these warnings aside, here's the stats on who came:
Design Engineer ############################## 61%
Design Eng. Mgr. #### 8%
CAD Engineer ########## 19%
CAD Eng. Mgr. #### 8%
Academic 1%
Business/Mrktng Mgr. 1%
Other # 3%
The types of companies they were from:
Wireless/Telecom/Modem ############################ 57%
Computers/Peripherals ################ 32%
Semiconductors ###### 13%
Audio/Video/Games/Appliances ###### 13%
Indust./Aerospace/Defence ## 5%
Medical 1%
Other ## 4%
The types of designs these engineers are creating:
Standard Cell / Gate Array ################################ 65%
System-On-A-Chip ################ 32%
Full Custom ##### 10%
FPGA/CPLD #### 9%
PCB # 3%
Multi-Chip Module # 2%
The speed, size, and process of the chips they're designing:
1 - 99 MHz ############ 24%
100 - 199 MHz ###################### 44%
200 + MHz ################ 32%
1 - 100 Kgates ######## 16%
101 - 500 Kgates ############ 25%
501 -1000 Kgates ############## 28%
1 Million + ############### 31%
above 0.35 um ## 5%
0.35 um ##### 10%
0.25 um #################### 41%
at or below 0.18 um ###################### 44%
Their design flow (COT means they're doing their own place & route):
ASIC design flow ############################## 59%
COT Cadence P&R ########## 20%
COT Avanti P&R ########## 19%
COT in-house P&R ### 6%
COT "other" P&R ## 4%
And the fabs and/or FPGAs they're designing:
In-House Company Fab ############### 30%
TSMC ############ 24%
IBM ######## 17%
LSI ####### 14%
Texas Instruments ##### 11%
UMC ### 7%
Lucent ### 6%
STMicroelectronics ## 4%
VLSI, Toshiba, NEC # 3%
AMI, Samsung, Fujitsu,
Charter, Intel, Epson,
Mitsubishi, National 1%
Xilinx ####### 15%
Altera #### 9%
Actel 1%
So, in a nutshell, it was mostly serious, high-end chip designers at last
month's SNUG'00. (A few years ago, I was a keynote speaker at both the
Cadence and the Mentor User's Group meetings. What I found there was these
conferences were dominated by SysAdmin guys and PCB designers -- with very
few actual chip designers attending. I'm proud to say that SNUG had a good
69 percent of its attendees were designers. Cool.)
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