( DAC 99 Item 50 ) ----------------------------------------------- [6/25/99]
"Product: Summit's Visual Testbench Rating: 1 Gator (out of 4)
Another product to help designers solve their verification woes.
This tool allows users to graphically capture timing diagrams and
use this data for documentation, generation of test vectors, interact
with the simulator, and capture simulation results. It's somewhat
similar to the Chronology tool as well. I'm not impressed with a
graphical waveform capture tool for million-gate designs since it
lacks concurrency features, random test features, and a much higher
level of abstraction. This tool might be of use to designers who are
doing small CPLD designs and or work mainly using schematic design.
Otherwise, its a waste." ( http://www.summit-design.com )
- an anon engineer
"SynaptiCAD's TestBencherPro:
They are competing against Chronology's Quickbench testbench
generation tool. SynaptiCAD's tool generates a Verilog testbench
from a waveform timing diagram. The waveform editor looked very
simple to use. I was impressed by the ability to load up a waveform,
move one of the input signals and then rerun the simulation to see
what you get. The tool is obviously designed to help debug small
blocks of code. http://www.syncad.com "
- an anon engineer
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