( DAC 99 Item 47 ) ----------------------------------------------- [6/25/99]
"This year I decided I would ignore the big flashy booths in the middle
and walk around the edge. Wow, was there some interesting stuff!
Take a look at HDAC. ( http://www.hdac.com ) I spotted their stand
in the far corner. They do static functional RTL verification that
does quasi model checking which seems very easy to use and appears
to actually work (in demo, of course.) They said Tandem and Cisco
are currently using their tool, 'Solidify'. It a different approach.
There are no test vectors in Solidify. 0-in and friends generate test
vectors that they feed to an internal simulator. For Solidify, you
write 'properties' in their HPL (which is Verilog with 4 additional
operators) to explain how your block works. (Their rule of thumb is
5 to 10 lines of Verilog typically translates to one 'property'. But
the specific metric they gave was one 12 kgate block, 8100 lines RTL
Verilog, had used 156 'properties' -- each 'property' covered 52 lines
of Verilog.) Then you use Solidify own 'properties'-oriented code
coverage utility to find what you're missing. Coverage is a separate
analysis, so it doesn't load down the tool, and it does incrementals.
It then lets you write new 'properties' to cover what you missed.
Currently, it's block level only with a 25 kgate per block capacity.
I liked what I saw. I cannot comment on the tool hands-on as yet,
but I'll keep you informed."
- an anon engineer
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