( DAC 99 Item 41 ) ----------------------------------------------- [6/25/99]

 OLDE FASHIONED ATPG, MEM, & BIST:  Although commonly used, these types of
 test for manufacture tools didn't make the big news like they used to at
 past DACs.  Only a few engineers talked about them.  Guess they're pretty
 much 'solved problems' in EDA (like simulation and basic synthesis.)

    "LogicVision seems to have good stuff for logic & memory BIST.  They
     seem to be ahead of their rivals."  ( http://www.logicvision.com )

         - an anon engineer


    "ATPG:

     Synopsys TetraMax is the next generation of Test Compiler.  Synopsys
     claims that it's intended to handle larger designs (1.5M+ gates).

     EDA Direct and ATG Technology where also at DAC and gave me business 
     cards.  ATG was promoting sequential ATPG.  ( http://www.atgtech.com )

     I ran into a guy named Al Crouch at the Mentor's Design-For-Test
     booth.  He clued me in on a bunch of scan chain problems, so I feel
     obliged to put in a plug for his book "DFT for Digital IC's and
     Embedded Core Systems".  Al definitely had a strong opinion that
     Synopsys' Test Compiler is an inferior product.  (Probably why
     Mentor Graphics hosted him at their booth).

     Here are the scan chain gotchas he told me to watch for if we allow 
     Avanti Apollo P&R to restitch the scan chain:

        1) Apollo will not recognize separate clock domains when it
           restitches.  It simply routes from flop to nearest flop without
           regard to the clock.  To get around this you need to put each
           clock domain on a separate scan chain and explicitly tell Apollo
           which registers are on which chain.  (I think that putting each
           chain on it's own enable facilitates this.)

        2) We cannot allow Synopsys to put buffers along the chain.  Apollo
           ignores them, routes flop to flop, and leaves the buffers and
           inverters hanging.

        3) Apollo does not have any sense of timing, so when it restitches
           and routes to the flop next door it could cause hold violations.
           Al mentioned a design he had with about 5000 flops.  Apollo
           introduced 3000 hold violations.

     Email Al_Crouch@prodigy.net w/ questions.  He was a really nice guy."

         - an anon engineer