( DAC 99 Item 32 ) ----------------------------------------------- [6/25/99]
IT'S DEJA VU ALL OVER AGAIN! After reading those user quotes that gave
the impression Synopsys Chip Architect and Cadence Ambit PKS are very
similar, now user first impressions of Avant!'s 'Jupiter' see it, too, as
very similar to Synopsys Chip Architect. And Avant!'s tool is designed
to feed into Synopsys' Design Compiler (which surprised me!) Gut reaction
without having seen Jupiter -- it just might be warmed over Planet-RTL.
When the going gets tough, many times the tough will change their name.
"Avanti's Jupiter: This is Avanti's answer to Synopsys' Chip Architect.
It addresses the synthesis/place and route timing closure problem by
doing floor planning before synthesis. The tool takes in RTL code, a
TDF constraint file, and library information (will accept .lib format).
The RTL code is linted and then pre-synthesized. (RTL Explore,
previously Verilint, is embedded.) The tool produces a floorplan,
custom wireload models and a Synopsys constraint file. From there you
go directly to Design Compiler. Optionally you could use their VDSM
(very deep sub-micron) synthesis tool, but I'm skeptical because their
salesmen didn't seem very excited about that capability. Finally
we've already got Apollo's place and route. Jupiter requires ("works
better in") a top-down design methodology."
- an anon engineer
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