( DAC 99 Item 31 ) ----------------------------------------------- [6/25/99]
"Tera Systems demonstrated their RTL partitioning tool to automate
structured design for optimization of performance and density.
According to the makers, the tool provides feedback which should
lead a designer to optimize HDL code rather than rely on the less
productive physical optimization of inferred logic. Could be worth
a closer look. ( http://www.terasystems.com ) I also heard that
Aristo had something similar, but I did not get a chance to see it."
( http://www.aristotech.com )
- an anon engineer
"TERA SYSTEMS
This is a RTL-level floorplanner. It offers RTL area and timing
estimation. Automatic RTL partitioning. Hierarchical area and
timing budgeting. Hierarchical chip and block-level floorplanning.
Routing estimation. RTL in-place optimization. Hierarchical design
management.
This tool is written for the front-end designer. They write out
files that drive Synopsys for synthesis and Cadence and Avanti for
chip assembly. This tool is available now."
- an anon engineer
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