( DAC 99 Item 28 ) ----------------------------------------------- [6/25/99]

    "Cadence's Envisia (Ambit PKS) - This presentation also emphasized
     single-pass timing closure.  It showed how system-level constraints
     were used throughout physical design:

              Floorplan
              Block place
              Power plan
              Standard cell place and optimize
              Clock tree synthesis
              Delay optimization
              Power routing
              Clock routing with power and ground shielding
              Final routing
              RC extraction

     It's clear that Cadence is solving deep sub-micron issues with this
     approach.  It also makes sense to incorporate timing at all levels.
     However, the flow is complicated compared to Magma's."

         - an anon engineer