( DAC 99 Item 14 ) ----------------------------------------------- [6/25/99]

    "Synopsys EPIC demonstrated their Cedar and Arcadia tools for 'Third
     generation physical verification and extraction'.   First generation
     tools ran on flatten designs, second generation do hierarchical but
     impose methodology restrictions.  Third generation tools used abstract
     views to increase flexibility and facilitate verification re-use, i.e.
     if an instance of a block has been DRC'd then other instances will not
     be checked.  Such abstract methodologies facilitate verification of
     up to 500 million transistors.  A final hierarchical run is required
     to ensure no violations are overlooked.  Distributed processing is
     possible with Cedar.  Accelerated symmetric comparison of parallel 
     circuits gives a 3X-50X runtime improvement.  Cedar took 1 minute to
     run 98 DRCs (200+ operations) on 60K transistors.  In abstract mode
     it took just 18 minutes to run these DRCs on 7 million transistors.
     It took 9 hours to run this job in flat mode.  Synopsys claim to have
     a translator for Dracula and Hercules runsets.  http://www.epic.com

     Cadence left me with no confidence that they will be a key player in
     the extraction/LVS/DRC/ERC arena as we look for a 3rd-generation
     alternative to Dracula. 

     Pathmill now has a CTX option for cross-talk analysis."

         - an anon engineer