( DAC 99 Item 11 ) ----------------------------------------------- [6/25/99]
"CadMOS Suite Demo: PacifIC noise tool. Includes device coupling
(Miller cap). Customers include AMD K6 and K7. Example: using a
peak-noise metric saw 4k failing nets. Using noise stability, saw
1 fail and 8 marginal nets. Interconnect model: RLC. Input is Spice
and bsim3 models. Logic/timing constraints entered via TCL files.
Could also be used in estimation scenarios, or as a custom design aid.
Runtime (based on examples shown in suite) appears strongly based on
number of transistors. 2M tx's in 21 hours on ultra 60. Required
2GB, about 1M cross-coupling caps. Provides some flexibility in
analysis (e.g., just do coupling, ignore R's.) Uses logic constraints
only on hazard free signals. (I think you have to assert that things
are hazard free). Key idea: noise stability lets you fix noise
problem by loading up output of receiver. ( http://www.cadmos.com )
Ultima Suite Demo: Nautilus-SI. Signal integrity "at 0.25micron".
Plans: Nautilus-PV for 0.18, incl. parameter variation. Nautilus-LM
for 0.13, include L's. Noise failure determined purely on a noise
margin/voltage basis." ( http://www.ultimatech.com )
- an anon engineer
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