( DAC 00 Item 48 ) --------------------------------------------- [ 7/13/00 ]
Subject: Avanti Lynx-LB, EPIC CoreMill, Circuit Semantics, Cadence TLA
ALMOST, BUT NOT QUITE: With all this talk about analog synthesis tools at
this year's DAC, lost in the discussion is a set of related analog tools
that have been around the EDA world since 1998 that also take SPICE and
GDSII as input and reverse compiles them back to Verilog gates.
"Avanti, is now widely marketing a tool it got from the Compass
aquisition called Lynx-LB that REVERSE COMPILES full-custom block
implementations (i.e. GDS-II files) back into synthesizable Verilog or
VHDL RTL! Formalized Design also offered a reverse compiler that reads
in EDIF or SPICE files and regenerates RTL Verilog or VHDL. And it's
rumored that Cadence and Sagantec might be working on something similar.
Ostensively such tools are to make design migration of old IP into new
applications doable -- but now what's to stop a Cadence or Synopsys
Consulting Services or even your TSMC support engineer from using these
very same tools to migrate your hot IP into their own cache of designs?"
- from the DAC'98 Trip Report ("In Lawyers We Trust")
Synopsys EPIC Coremill and Circuit Semantics DynaBlock also had similar
reverse engineering / reverse compiling functions in 1998. Formalized
Design wasn't at this year's DAC. And, a few weeks after DAC, Cadence
publically joined the reverse compiler club with TLA:
"Transistor Logic Abstracter (TLA) Cadence
Model generator
Abstracts logic-level Verilog functional models from SPICE or SPECTRE
transistor-level netlists.
Applications: Accelerated simulation, equivalence checking, and
emulation of transistor-level-model custom blocks and silicon IP
Comments: TLA works with static CMOS, ratioed logic, precharge/domino
logic, pass-transistor logic, and cascode-voltage-switch logic (CVSL)"
- Jim Lipman of TechOnLine
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