( DAC 00 Item 47 ) --------------------------------------------- [ 7/13/00 ]
Subject: Barcelona, Antrim, NeoLinear, Tanner, ComCad, Silvaco, SPICE
WHAT'S GOOD FOR THE GOOSE: Seeing all the sucess in the digital world for
synthesis-like tools, this year at DAC a number of "analog synthesis" type
of companies came to the forefront. Way back in DAC'95, some university
types from Eindhoven, Netherlands gave a talk in Session 25 about genetic
algorithms being used for analog synthesis. A year later, Sony and Cadence
made press hinting at analog synthesis. Then, in 1997, the University of
Cincinnati announced VHDL-AMS Synthesis Environment (VASE), an analog VHDL
synthesis tool suite based on Carnegie-Mellon's ASTRX/OBLX tools. Then at
DAC'98, Anasift hinted at an analog synthesis tool. In July of '98 there
was more VASE talk. In Nov. '98, Neo Linear hinted. At DesignCon'99, Ron
Gyurcsik, director of Cadence Design Systems' analog and mixed-signal group
said "Analog synthesis is always the holy grail. It's tomorrow's solution.
It's not really there." Four months later, HP EEsof announced its "RF
Compiler" that created analog circuit from behavioral descriptions. Six
more months later, Antrim announced, but in that same EE Times article, Gary
Smith warned: "Yes, we're going to automate analog design, but it'll be 2004
to 2006 before we get there." Then in late Febuary of this year, ex-Cadence
CEO and EDA playboy came out of EDA hiding to back Barcelona; bringing us
to the analog synthesis explosion at DAC'00.
"CADdexterity sells CAD to facilitate custom design of large analog
blocks. It can generate an initial layout from your schematic, then it
only allows you to make legal layout changes, understands splitting or
folding or merging transistors, can do simple logic optimization, and
can do compaction.
Antrim Design Systems and Comcad sell tool that takes as its input a
SPICE netlist and a description of the design requirements (entered
either in a script or GUI). It automatically sizes the transistors to
meet the requirements.
Barcelona Design sells a tool similar to the two above, except that you
don't input a netlist, you choose from a library that they provide.
They have 50 different netlists for an op amp. They currently only do
op amps, inductors and resonators, and currently only output a SPICE
netlist. They plan to do PLLs and switched capacitors, and also to
output GDSII.
NeoLinear takes a specification and a stick layout/schematic, and does
both the sizing of transistors and the final layout. They say these two
steps normally take about 70% of the time in doing an analog design.
Tanner continues to sell a lot of cheap PC based analog design tools.
France's Dolphin Integration has a family of PLLs that it customizes for
your process and delivers GDSII, SPICE netlist and other documentation.
BTA Technology and Silvaco sell tools that makes SPICE models from
measured data."
- an anon engineer
"Most interesting new spin - everyone suddenly now does Analog Synthesis!
What a great concept; this capability has only been in commercial SPICE
simulators for the past 15 years - it is pretty cool that they just
invented it.
The folks at ComCad in Germany had a very low key booth to discuss what
is basically their SmartSpice/PSPICE optimizer product with their own
schematic capture tool.
The Antrim guys were a bit on the arrogant side and refused to schedule
me a demo as I was only a consultant and not planning to buy their
product; however their floor demo showed time based optimization with
reasonable corners. The tool could synthesis design and create
behavioral models for some standard mixed signal and analog topologies.
To play it safe - they did the right thing and output Verilog D
/ Verilog A and Verilog AMS. The big problem is the behavioral models
and the resulting simulation characterization of the design could not
be obviously back annotated from layout with parasitics and then the
resulting design undergo re-optimization while maintaining the
parasitics and generate a new behavioral model. Additionally, the
synthesized blocks did not take into account nor specify any application
constraints on implementing the design in silicon (proximity to other
blocks, current density requirements, orientation.) They assume that
the process corners is sufficient information -- so there is no way to
reality check on the IP blocks created. Since only a few standard
topologies were supported -- the automated synthesis of major mixed
signal blocks and their associated Digital sections (i.e. PLLs, data
converters, transceiver) do not really yield any designs that are
achievable in a reasonable time as the test suite generate is very
tedious for all aspects (DC/Transient/AC/Noise/Harmonics) of the design
flow. Additionally, the results created by the characterization do not
yield intermediate fail data so if multiple model corners and analysis
types are chosen -- very little info on the corners that don't work are
reported. I think for folks who need the Verilog A/Verilog AMS outputs
who are traditional MTB clients may like it -- but it is too early for
real analog guys. In about a year these folks may have something to
really look at.
The NeoLinear product was pretty cool -- they had a method that with a
decent and flexile gui they could do high speed device optimization
utilizing a new stopping algorithm for determining directions not to
pursue (a feature not found in the current old technology SPICE
optimizer). They also have a very cool distributed simulation engine
( pricing and licensing model TBD.) Unfortunately, most companies
have such bad network traffic, I don't think it can be used effectively.
It currently does not do the cool stuff for multi-threaded so those of
us who are fans of big multi-processor compute servers have to wait.
They also have a hook into auto layout generation from the schematics
that deal with Analog things like shielding and cross-coupling. This
is a great alternative for the Analog custom stuff as you don't need
several 10K-100K chunks of money for non-migrate able P-cell development
and their layouts can even pass LVS with a hierarchical tool (Calibre
and Hercules). The tool can even resimulate and optimize after post
layout extraction. The big limitation is that the tool outputs
SPICE/CDL as the base mode - no high level stuff like Verilog A or
Verilog AMS. The tool, unlike Antrim, is targeted toward mid-senior
level engineering who want higher productivity rather than replacing
high cost head count with new brains (recent grads) and "smart tools".
This analog stuff is still magic for getting the Si to work and this
tool does a great job of getting higher productivity from Sr staff who
can't work on enough projects as they are bogged down doing n-teenth
circuit simulations and manually being the "stopping algorithm break
point". Other than a good designer and Silvaco's Multi-threaded
SmartSpice and their process based "Clever" RC extraction product for
open topology, it is the only practical solution available in June
2000 to June 2001. Definitely folks to keep an eye on them - it is not
glorified MTB. It appears to be real analog device synthesis."
- an anon engineer
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