( DAC 00 Item 42 ) --------------------------------------------- [ 7/13/00 ]

Subject: Hercules II, Calibre, Cadence Assura/Dracula, Numeritech OPC

PHYSICAL VERIFICATION & OPC:  A billion years ago, before Cadence made it
big on Gateway's Verilog-XL simulator, Cadence at one time had one very
kick ass DRC tool called 'Dracula'.  For those of you who are frontend guys,
a DRC tool is the backend's equivalent of a linter.  If you were doing any
GDSII tweaking, you simply HAD TO HAVE a killer DRC tool to make sure you
weren't messing things up horribly with those polygons.  Not DRC (Design
Rule Check) and LVS (Layout vs. Schematics) tool are lumped under the fancy
important sounding title of 'Physical Verification' tools.  It's still all
the same stuff -- check to see that you didn't screw up your chip with that
last set of changes you put in.  The players in this market are Cadence
Dracula/Diva/Vampire/Assura, Avanti Hercules II, and Mentor Calibre.  The
Numeritech OPC is a tool that deals with lithography blurriness around
sharp edges once you start going at/around 0.18 um.

   "The best tool demo I saw was for Mentor StreamView, a simple, easy to
    use GDS-II viewer.  I liked the way to works with Calibre to highlight
    DRC errors."

        - an anon engineer


   "Physical Verification

    There are supposedly three players in this arena - Mentor, Avanti and
    Cadence.  The Mentor folks showed slides indicating that they are the
    largest installed base now - and their new version of Calibre actually
    kicks butt pretty well for people doing full custom design and IP
    development.  They added some nice hooks into their OPC and PSM flows
    to make it seamless to get to from the verification tool.  Also they
    have really improved the error / short identification capability
    especially on the new complex trench isolated and 3-well processes.

    As a big aid in dealing with large databases - they built a new viewer
    so you can bring up big designs for debug (even if they have dummy metal
    and OPC data) without a technology file real quickly.  Their StreamView
    product is about 10x faster than ICStation & has about 30X on Virtuoso.
    It even allow you to load greater than 2GB files on a 32-bit OS.  This
    saves a ton of time over doing a new OS port.  The product is still 
    real strong but I am not sure of the marketing numbers on it which show
    over 50% of the market.

    Avanti is now playing major catchup in the full SOC physical
    verification - the new HERCULES2 which added a flat engine to help stuff
    compare helps a bunch - however as the company has almost no functional
    AE support - the transition to the new tool is hard.  You don't get the
    same answers with old data and an old control file with old program and
    the new version.  They are adding in some short finding tools that are
    now only about 5-6 months behind in capabilities from what Mentor
    has - except theirs is still very unstable in the umpteen versions of
    Cadence floating around.  The Mentor stuff is rock solid.  These guys 
    have about a 6 month window to play catch up and then if they don't get
    there they will be out of the game for any NON-APR clients.  The
    Hercules2 hooks into Apollo and their suite is nice and tight and you
    cannot drop Calibre into the Apollo flow and get any good results.
    However they did this at the cost of not addressing and being useful for
    the custom IP development world.  The Avanti marketing slides indicate
    that they also have over 50% of the market.

    The Assura product from Cadence is their latest attempt to get back into
    the physical verification game.  They are obsoleting Vampire (what a
    surprise) and plan to run Diva and Dracula clients into this same black
    hole.  The tool does not understand Hercules concept of hierarchy and
    block boxes, nor does have a standardized runset control language - it
    is a Cadence 4.4.5 product so your rules are in the weird Skill/TCL
    language - which will probably have to be re-written each time you rev
    the kit just like with Diva now.  No info on short checking
    hierarchically, missing pin probing, or merged netlist probing
    (Verilog/CDL).  The biggest draw back is they still recommend and advise
    that you run from the "open" Cadence environment.  That means without
    checkin and checkout being done.  The result is if you kick off a 3-4 hr
    DRC, LVS, RC Extract job - the job runs from a "snapshot" of the data.
    If someone checks in a cell in the design prior to the verification
    being completed (this happens more often than you think in multi project
    groups) - when the data comes back it may flag or tag structures that
    aren't there.  The folks at Cadence doing the demo suggested the
    solution being "just buy some extra licences, and when the cells get
    checked in, kick off an extra job and look at the errors for that block
    separately".  They also claim to interface to an OPC solution, however
    they did not have info on how generate the base information needed for
    the flow and indicated that typically the resulting databases could not
    be viewed - so you should just go to cut the mask and see if there are
    problems.   Sometimes they just don't understand..."

        - an anon engineer


   "Numeritech sells a tool to add phase shifters to masks.  At very small
    feature sizes, you need a phase shifter on every other opening in the
    mask.  The problem is that "every other opening" might be clear when
    dealing with long parallel lines, but in typical layouts where lines
    appear and disappear and have turns, there is no way to always do that.
    For example, a critical net is not allowed to have a "T" in it (a "T"
    has three areas touching it, so there's no way to put shifters on every
    other one).  Numeritech (Numerical Technologies) makes software that
    checks for illegal geometries and then processes the maskmaking data
    for phase shifters. Currently they only do polysilicon (the gate level).
    Since poly is typically used only within cells, this means that you can
    run their DRC on individual cells, and if the cells are clean it's
    unlikely you'll have problems at chip level.  Dealing with metal levels
    is another story.  It's not clear who will solve this problem - routers
    when they design the metal, compactors after the routing is done, or
    someone like Numeritech when you go to make the mask.  Numeritech is
    working with Cadence's Place and Route researchers.

    Mentor is now going into competition with Numeritech, selling software
    for optical proximity correction and phase shifting."

        - an anon engineer


 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)