( DAC 00 Item 41 ) --------------------------------------------- [ 7/13/00 ]
Subject: Prolific, Cadabra, Silicon Metrics, Circuit Semantics, Sagantec
DOUBLE DATING: In the standard cell world, there's an odd pair bonding
where customers tend to use Prolific's suit of standard cell generation
tools with Circuit Semantic's characterization tools -or- they use
Cadabra standard cell generation with Silicon Metrics characterization.
There's no technical reason why this is, but it's the way the customers
mentally place these four companies as two couples. Odd. Library
Technologies Inc. also plays in this space and a few people noticed
Sagantec's process migration, too.
"It amazes me that companies are still creating new compaction-based
layout synthesis tools, because Cadabra already has some 45 degree
support and that's what it takes to make dense layout (I have full
45 degree capability with no need for compaction, of course).
Synthesis tools with rectangles only (Sycon, Prolific) are a dime a
dozen."
- an anon engineer
"Cadabra - a physical library creation toolset which wasn't very
applicable to our current business model."
- an anon engineer
"Circuit Semantics:
Their salesdrone said that their DynaCell performed characterization
for Synopsys synthesis, PrimeTime, Power Compiler, Cadence TLF &
Verilog. DynaCore does block characterizations supposedly on up to
1/2 million transistors and outputs to PrimeTime and Pearl. It's
an all paths model. Their DynaModel takes transistors in and puts
gate-level Verilog netlists out similar to Avanti's tool."
- an anon engineer
"Silicon Metrics - They provide physical design library manipulation
tools that determine "Instance Specific Operating Points". Their tools
apparently enable tweaking of the libraries and instantiation of library
pieces based on the particular context of each instantiation of a cell.
I believe their tool only works with OLA library formats and few
commercial libraries support the "Open Library API (Application
Programming Interface). OLA as yet. I don't think [ EDA Co. Name ]
supports OLA, so I don't think we can use these tools yet. We should be
talking to [ EDA Co. Name ] about supporting OLA."
- an anon engineer
"* Cadexterity seems to be back on the scene - they have a "layout
productivity tool" that would be a competitor for L-Edit (at the
right cost)."
- an anon engineer
"SiliconMetrics. Loved these guys. I love anybody who sends me work
mail from an aol account. Makes it seem like they're working out of
their garage.
These guys really have the religion on unified delay calculation.
They've got a library solution that might make unified delay calculation
less of a pain for library generation. They've got a spiffy bolt-on
solution for Primetime for unified delay calculation. And while I'm not
sure I'd want to give this to all my designers, they've got a gizmo that
will burp out a critical path with parasitics for HSPICE simulation.
Cool."
- an anon engineer
"Library Technologies Inc. sells a library characterization tool, but
also does circuit optimization. It resizes drivers in COT designs in
order to reduce power. They claim huge power savings.
Silicon Metrics is also sells library characterization software. Their
thing is to characterize delays for each instance in your ASIC based on
physical location (local temperature and supply voltage) and create a
separate delay for each and every instance. It gets the temperature and
voltage drop information from Simplex. You then feed these delays into
Primetime using the OLA standard. They say this prevents you from having
to assume that all gates everywhere are at worst case supply drop and
temperature, so you can squeeze more speed out of your process."
- an anon engineer
"The 3 Lib Tech tools that interested me
LowSkew a clock network optimizer which generates a
zero skew network by sizing the drivers. Used
for reducing power, reducing clock noise, jitter.
LowBounce a ground bounce minimizer for designing robust
and quiet IO buffers. It adjusts the predrivers
to control dI/dt on the supplies with realistic loads.
CellOpt a timing/power optimizer can reduce peak currents,
IR drop, electromigration constraints, and cross-talk
I don't know how good they are. It appears that Lib Tech is a
one man shop. The upside is with a small budget, we could probably
get great support from him. The downside is it's a one man shop.
He could be gone tomorrow."
- an anon engineer
"Library Technologies' power optimization tool doesn't look very useful
to me because my layout synthesis tool will be creating cells in
seconds. Taking hours to size the transistors (even for a single-stage
gate, e.g. AOI) makes the speed of my tool kind of pointless. "Just
buy more SPICE licenses" is not the kind of answer I want to hear."
- an anon engineer
"Worst DAC freebie: Sagantec frisbee. It doesn't stay open or fly very
well. Kind of a disappointment because it looks good."
- an anon engineer
"Sagantec - Hurricane, a product to move the hard core, intact, to other
geometries. Layouts are claimed to be smaller than a shrink. The
software intelligently migrates the design. Xtreme, a product to tweak
a design to optimize if to reduce interconnect capacitance and cross
talk. They claim a reduction in cross-coupling capacitance of 40% for
.35 micron and better than 50% for .25 micron and below. This could
speed up and reduce power on the chip."
- an anon engineer
"My boss might like Sagantec Si-Clone if they deliver. We've been trying
to migrate the mother of all processes. I will welcome them if their
stuff actually works."
- an anon engineer
"* DSM Technologies, Inc. -- They have a really neat graphical tool for
specifying process rules. Some companies have apparently signed on
to use their tool to produce their process rules documents. The
information is entered in a pictorial form with annotations specifying
rules related to spacing, width, etc. They output a rules document
in PDF which describes the rules. More importantly, they can also
produce run decks for Dracula, Diva, Hercules, and Mentor's tool
(forget the name). We suggested to Cadabra to consider reading their
rules format in directly, instead of having a user hand-type it."
- an anon engineer
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