( DAC 00 Item 40 ) --------------------------------------------- [ 7/13/00 ]
Subject: Bullish On Cadence & Cadence NDA 'Integration Ensemble'
BULLISH ON CADENCE: First let me vent. I've gotta rant. It's coming...
It's coming... Why the hell did Cadence, 21 months ago (Sept. 98), drop
$260 *MILLION* in cold hard cash to get that Ambit PKS physical synthesis
tool and the bloody thing *STILL* doesn't *WORK*??? What is 21 months and
a quarter BILLION dollars supposed to get you??? The backend is your home
turf, guys! Come on! You guys should have been kicking ass in this market
with Synopsys being the one playing catch up. Do you know how pathetic it
is to have a 21 month lead and you show up at this DAC and you still don't
have one measely customer tape-out??? Is PKS a re-enactment of Vampire?
And since we're bitching up a storm here, could you please, PLEASE get your
marketing to stop it with the weasil games? Last year they babbled about
'Nano' being the future. Then it's become 'PKS'. Then it's Italianifying
all the bloody product names. "I'm Assura I Cierto do not know what the
hell Envisia is supposed to mean." Where's my bloody Verilog-XL? Then its
'PKS-II'. Nope make that 'SE-PKS'. Or is that 'PKS-SE'? Sorry, that's
'SP&R'. Oops, now its 'Integration Enemble'. And 'SE-SI'. Oh, and by the
way, we're going back to our pre-Italian names...
Is it too much to ask you guys to PLEASE make up your damn minds and to stop
continually changing your marketing stories??? I'm used to EDA marketeers
lying to my face, but the Cadence guys do it so unabashedly, it's insulting.
Do you guys have secret bets on who can get away with the biggest, most
ridiculus lie you can pitch to a customer???
Aaahhh... That felt good...
Now that I've gotten that out, I'll tell you why (to use the Wall Street
lingo) I'm bullish on Cadence. No, I'm not talking stock talk. I don't
care about that. I'm talking tech talk. In the old golden Costello days,
Cadence used to pitch a new tool every month. Many of them were vaporware
that Cadence was pitching to guage customer interest or to mess with a
competitor, but the remaining part of the time a new tool (or set of tools)
would eventually pop out of the Cadence R&D pipe. This all stopped when
Joe caught the 'Outsourcing Viris'. It was ugly. New tool development
dried up because the head honcho put the writing on the wall that he wanted
to see more and more consulting dollars filling the Cadence coffers. This
nasty little Outsourcing Viris eventually got Joe booted. The FAM debacle
with the Outsourcing Viris layoffs ousted CEO Jack Harding. That whole time
the marketing weasils chatted up Outsourcing until, oddly enough, Ray
Bingham (whose background is in hotel finance) became the Cadence CEO.
And then the weasils weaned back on Outsourcing. They switched gears to
concocting absurd techie talk. Now Cadence is openly hinting at spinning
out consulting as it's own business. This means that Cadence is slowly
reverting back to being an EDA company that actually makes money from
better marketing and (more importantly) better EDA tools themselves. Yes!
(But it means we're gonna have to wade through even more creative Cadence
marketing hooey, to figure out what their R&D is actually making for us.)
Here's what the Cadence technology mill has churned out recently. Much of
it is mixing and matching of their existing tools. HECK is their new
equivalecy checker that they demo-ed with their TLA tool. They demo-ed
their new AMS Designer product for complex mixed-signal design that
integrates the Spectre analog simulator with NC-Sim. Their 'Virtuoso CD'
is the IC Craftsman router plus a new auto placer. They touted ATS 3.0 has
Signalscan to the mixed-signal custom guys.
Verification Cockpit got 3 out of 3 stars from customers in another part of
this trip report. (Which was kind of funny. Cadence marketing talked up
Verification Cockpit at last year's DAC, so customers assumed it wasn't real
then. This year, the customers now believe it's viable and rave about it.)
They demo-ed NC-Sim with FormalCheck, their model checker. Now you can do
HDL queries. (Meaning you can write an assertion in their HDL style, and
it'll work with NC-Sim and Formalcheck.) Verification Cockpit with
Verisity! FormalCheck and NC-Sim can read "e". (NC-Sim, their dual-language
Verilog/VHDL simulator, was their 'slut' product matching up with anyone and
everyone.) NC-Sim with Denali. NC-Sim with Synplicity. NC-Sim with ATS,
their MOS digital simulator. NC-Sim with AMS Designer. NC-Sim with SPW.
NC-Verilog, NC-VHDL, and of course, our trampy little NC-Sim all now run
on LINUX.
They claim that their SE-PKS has routing-based optimizations to predict,
measure and repair cross-talk induced errors while maintaining equivalent
timing performance. They also claim PKS has the means to forward annotate
this to layout and that they have "unified the data model from synthesis
through SI-correct routing." (I don't know if any customers have actually
tried this or if it's just a Cadence claim right now.)
VCC Felix is their system level design tool for HW/SW architectural
trade-offs similar to Mentor Seamless or Synopsys Eaglei. It uses Alta's
SPW to model wireless tranceivers and RF channel modes. VCC also has some
of that "communications synthesis" where it automatically partitions out the
logic that deals with interblock communications. (Ambit technology)
Their new Spectra-RF is much like Mentor ELDO-RF and does mostly RF time
domain analysis. Ambit-RTL's distributed synthesis is actually supposed
to work now and they're toying with low power synthesis, too.
There's a lot of Cadence swimming in this DAC Trip Report. Check out the
other sections.
"Cadence Integration Ensemble (NDA)
Integration Ensemble is the new name Cadence is using for their Nano
project. Nano merges SE, LDP, PDP, PKS, IC Craftman, and Genesis db
in one big does all tool. DP seems to be cleaned up inside of Nano.
Nano is very similar to what Synopsys showed us in physical. Very
hierarchical. At RTL, break design into blocks like Chip Architect.
Nano's FlexRoute is better because it pulls out each block's pins and
connected logic for a detailed global block pin assignment and route.
No estimate, detailed. SE-PKS works as Physical Compiler to synth
to placed gates with the Qplace timing engine. Internal handoff to
WRoute. Tck/Tk support, no SKILL. Three modes: flat, time-budgeted
hierarchical, Nano hierarchical. Say FCS in November. Not feasable."
- an anon engineer
"Nano: looks very promising and interesting. The most complete
integration of state of the art P&R including DSM features with a block
based design flow. Questionable is the rather closed GENESIS DB.
Nano's weak point seems to be the timing verification support within
the Nano block approach (it all looks like done by backend minded
people, (surprise!))"
- an anon engineer
"There are four fundamental steps in the new design flow Cadence is
proposing. The first is global wire planning and routing. The input to
this stage is RTL code and block-placement and pin information. Some of
that data may be very preliminary, allowing for the exploration of
architectural alternatives.
The global wire-planning and routing stage assigns wires to layers,
buffers wires, runs global routing and does pin optimization. Global
routing is a detailed and presumably final interblock route -- not an
estimate.
The second stage, communications synthesis, is based on technology
acquired from Ambit. Added to this is an ability to automatically
partition out logic that deals with interblock communications. That's
what the new Cadence software will synthesize first, and separately,
from logic that is strictly internal to the block.
In the third phase, which Cadence calls block "physically knowledgeable
synthesis," the internals of the blocks are synthesized, but not with
traditional wire-load models. "We have a complete physical P&R model
built into the synthesis tool," said Richard Brashears, vice president
of R&D for Cadence's Ambit group. "It does a gate-level initial
placement, and then all the trade-offs in synthesis are done in the
context of logical and physical transforms."
The final fourth stage is final assembly and layout optimization. This
includes intrablock routing with Silicon Ensemble and chip assembly with
IC Craftsman."
- from EE Times (May 17, 1999)
"Last year Cadence's Physically Knowledgeable Synthesis (PKS) sounded
superior to Synopsys. It did detailed routing and addressed crosstalk,
resistive self heating and electromigration, none of which Synopsys
could do. Since then, Synopsys has had number of customers who
successfully used their tools, starting maybe six months ago, and
Cadence finally got out a single design last month. I attended the
demonstration of Nano, which is the new hierarchical version of PKS due
out in November. It sounds similar to the Synopsys tools. It will be
using the new Genesis binary database rather than LEF/DEF. The API for
Genesis is public. Nano will use HyperExtract rather than the Clover
tool."
- an anon engineer
"I'm a bit spectical about the converge of the PhysOpt flow, as long as
Synopsys doesn't use its own detailed router. Maybe I'm prejudiced, but
I also don't believe in the Cadence PKS solution, either. I'm doing
business with Cadence since many many years and they have already
announced so many software solutions that never worked. They are quite
good in delivering point tools such as Verilog, Dracula, Virtuoso or
Spectre, but whenever they had to combine different domains, in this
case synthesis, P&R, timing verification, they had a lot of problems.
i.e. they have problems to reuse their existing tools. That's why I
expect that they will have problem to deliver a solution with a tight
intergration."
- an anon engineer
"Cadence continues to push everything towards Ambit. They take the
products that sell (DP, SE) and are useful and integrate them around an
Ambit environment. And TLF... Dumb idea! They should use .lib
We are using Physical Compiler, and it works pretty well. The Ambit PKS
eval we did was a disaster. PKS is a good year behind PhysOpt - PhysOpt
interfaced to LEF/DEF (SE) better than PKS did!"
- an anon engineer
|
|
