( DAC 00 Item 37 ) --------------------------------------------- [ 7/13/00 ]
Subject: A Cooley Technology 'Find' -- Prosper 'HybridMaster'
A VERY COOL IDEA: At first cut, you might not think much of Prosper Design
or it's 'HybridMaster' tool. It looks just like another physical synthesis
tool a' la Mentor 'TeraPlace' with some Aristo 'IC Wizard' thrown in.
What caught my eye in the poorly put together Prosper DAC booth was the very
innovative way their technology works. They spoke English haltingly, so
here's the understanding *I* got from talking to two of their engineers,
seeing their web site, and reading their literature. HybridMaster
sits in between floorplaning and your Avanti/Cadence P&R. It reads in
LEF/DEF/TLF/SDF and works as a hierarchical P&R management tool. And
here's the trick that caught me eye -- it allows you to completely flatten
your design so you can do Clock Tree Synthesis and Power planning and
*then* it RECOVERS your hierarchy for block level detailed/legal/yada/yada
P&R!!! Whoa! It's the best of both worlds. CTS and power grids are very
placement sensitive puppies. Yet the ever bigger *flat* designs will also
eventually be too big to do *flat* in P&R -- so you need a *hierarchical*
approach to get designs done in a reasonable time. Want to talk
hierarchical? HybridMaster can run across multiple workstations!
The other part that drew me more to them was that HybridMaster isn't a
concept tool. It's already been benchmarked by STMicrosystems on a real
chip and they had the raw data right there up on the walls (hand labeled
graphs and all) like a grad student's thesis being put together:
"Chip Description (STMicro)
Component Number : 51,000 Cells
Net Number : 54,000 Nets
Clock Nets : 7 clock Nets
Process : 0.35um, 5 layers
Soft Blocks : 3 soft blocks
For the test case that can be handled flat by P&R engine, HybridMaster
achieved:
~3x improvement in P&R run time
8% improvement in routing wire length compare to flat.
15% less loading for feed through net
Up to 30% Improvement in timing violation (pre-ipo)
Better die size
individual CPU runtimes averaged to ~35% of flat P&R runtimes
Reduced die size by 2.2% with DRC clean"
The benchmark histograms and graphs on feedthrough and wirelength and
"slack vs. number of violations" are kind of hard to share it in ASCII
here. Trust me, they looked good. http://www.Prosper-Design.com
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