( DAC 00 Item 36 ) --------------------------------------------- [ 7/13/00 ]

Subject: Tera Systems 'TeraForm' & Aristo 'IC Wizard'

THE QUIET COMPANY:  In the insurance industry, Northwest Mutual advertises
itself as "The Quiet Company".  In the EDA industry, Tera Systems should
advertise itself as "The Quiet Company".  They have a tool that's a bit
like Avanti's Jupiter or somewhat like Synopsys Chip Architect.  It's
a bit different though because Tera System's TeraForm is meant to work with
DC with an emphasis to re-optimize your source Verilog/VHDL RTL to solve
your timing convergence problems.  (Again, this isn't a placement optimizer
like many of Tera's competitors, it's an *RTL* optimizer.)  Sometimes users
lump TeraForm's approach with Aristo's block mindset.  Why?  I don't know.
They're distictly different tools and companies.

   "Tera Systems - Tera Systems is taking a different approach to physical
    synthesis.  Their approach is to re-partition the RTL description block
    structure into a physical block structure and then use quick and
    approximate synthesis and placement.  Their approach runs an order of
    magnitude or more quickly than other approaches, but will not optimize
    as well as other tools because of the approximations used in synthesis.
    I'm guessing the sacrifice in performance and/or area will be in the
    order of 5-10%, but they did not quote a number.  This is a good
    question for a follow up meeting.  Their tools must be calibrated to a
    standard cell library.  They're meant to work with DC.

        - an anon engineer


   "Aristo - There were distractions during the demo and the demo was not
    focused.  Aristo is taking an approach similar to Tera Systems with
    respect to performing a re-partioning of blocks to optimize the routing.
    However, they are working at the gate netlist level.  I'm not sure if
    they are doing routing since it didn't come up in the conversation and
    I didn't ask.  They also claim that partitioning the design allows them
    to perform routing more quickly and better.  Their target designs are
    several million ASIC gates and larger.  Potentially this company's
    approach will be very effective, but I don't consider a follow up a
    high priority."

        - an anon engineer


   "* Aristo:  Their floorplanner looks more solid, but no significant new
      capabilities."

        - an anon engineer


   "Aristo sells a floorplanner than has a channelless block router and will
    vary the aspect ratio of each block automatically so that there is no
    empty space between bocks."

        - an anon engineer


   "Aristo is too much block oriented.  (How many blocks is 15 million gates
    exactly...??)"

        - an anon engineer


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