( DAC 00 Item 28 ) --------------------------------------------- [ 7/13/00 ]
Subject: BIST -- LogicVision, GeneSys TestWare, Syntest
BEST BIST STUFF: LogicVision seems to clean up in the BIST category at this
year's DAC even though from the Dataquest 1998 numbers Mentor owned 27.7
percent of this market vs. LogicVision's 59.5 percent. Why do I say this?
Nobody, not one, mentioned Mentor's BIST from the 113 respondants to the DAC
survey, while lots talked LogicVision and a lessor number talked GeneSys.
One bad indicator for Mentor's 2000 market share BIST numbers.
"We're using LogicVision MEMBIST and Formality. So far MEMBIST looks ok
and Formality has been a winner. We are actively looking at most of
the vendors you mention, even Cadence for FormalCheck."
- an anon engineer
"We have used LogicVision BIST in one of our recent projects. In this
design the scan chains are used both by the BIST machinery and by our
on-chip (or in-core) debugger machinery, and this is clearly a problem
for the LogicVision tool. Also, the tool makes requirements on details
that seems to have little or nothing to do with testability. Things
like having to blast a bus into individual bits."
- an anon engineer
"Fujitsu used Logicvision's logic BIST tool very effectively. BIST,
which stands for Built-In-Self-Test, is most commonly used on RAMs
because the patterns are very repetitive and have high fault coverage.
The typical knock against using BIST for logic is that you quickly get
up to maybe 70% or 80% coverage and then it takes gobs of vectors to
eke out each additional percent. For example, if there is a zero detect
on an 32 adder output, random patterns would result in this signal being
active only once every 2**32 clocks. In the past, some people have
advocated starting the test with BIST, then doing extra vectors for the
tough faults. Logicvision has software that identifies where to add
extra test points (like a zero flag) so as to get high coverage with
fewer clocks. Fujitsu got 99% fault coverage with this tool.
Intel reports that there seem to be more resistive bridging faults as
feature sizes fall below 0.18 microns. They also think there may be
more opens in copper interconnect. They stressed the need for more
advanced fault models. We've been using single stuck-at fault models
for a generation because they are very easy to simulate. The speaker
talked about the need to model transition faults, path delay faults,
opens and crosstalk."
- an anon engineer
"LogicVision - It's been almost a year since I heard Logicvision's story
about logic BIST. I stopped at several DFT locations and none of them
has as good a plan and understanding for test as does LogicVision. I
was having doubts about going with them before the show, but I'm more
comfortable that LogicVision is a good choice going forward."
- an anon engineer
"Syntest - has tools for boundary scan insertion, fault simulation,
testability analysis, scan synthesis and ATPG, and memory BIST.
GeneSys TestWare - has a mix of products for boundary scan insertion,
memory BIST and other test related items."
- an anon engineer
"Logicvision has sold tools to insert Built-In-Self-Test (BIST) for RAMs
and logic for a few years. They now have a tool for adding BIST to Phase
Locked Loops (PLLs).
GeneSys is a competitor to Logicvision, but they provide test IP versus
a tool. They have IP for SRAM & DRAM BIST, boundary scan & logic BIST."
- an anon engineer
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