( DAC 00 Item 24 ) --------------------------------------------- [ 7/13/00 ]
Subject: Cadence Ambit-RTL, Synopsys Design Compiler, Meropa/Get2chip.com
ONCE MORE INTO THE BREECH: After a 10 year momba line of companies jumping
into and out of the RTL synthesis market (with IBM's Booledozer, Mentor's
Autologics & Autologics II, Cadence Synergy, and VeriBest being the most
notable), the olde it-never-took-off-with-behavioral-synthesis Meropa has
reformed itself into a new company called "get2chips.com" offering what it
now claims is better *RTL* synthesis. At DAC they had an impressive demo
where they claimed to have synthesized in 5 hours a 0.5 million instances
250 Mhz UMC design on a 32-bit 800 Mhz Pentium III Linux machine. Their
claims to fame are 1) they have three excellent ex-Synopsys R&D engineers
on staff, 2) their RTL synthesis uses only 1 kbyte of memory per gate while
Synopsys Design Compiler uses 4 to 7 kbyte per gate, 3) their synthesis is
linearly scalable (i.e. it synthesizes 3000 gates per minutes no matter how
big the design is), while DC works hierarchically, and 4) they've made
noises about doing physical synthesis, too. The only problem get2chips.com
faces is that there are no customers who have actually used their software
for a tape-out yet. (The get2chips.com guys tell me that they have one
customer who has taped out, but for some funny reason they never say who
that customer is...)
Anyway, missing tape-out aside, if 1/2 of what these guys say becomes even
partially true, I'll be one happy camper because it'll once again spur
serious competition in the RTL synth business! It's always good to have a
nimble little guy embarrassing the big guy into doing a better job.
Remember how the pre-Cadence Ambit caused Synopsys to significantly improve
Design Compiler? YES! As a customer, we won big time until that Cadence
big company aquisition pretty much killed Ambit-RTL spunk and innovation...
And it really says something embarrassing when still 2 years after Cadence
bought Ambit, one of the biggest customers using Synopsys Design Compiler
is Cadence's own design services division! ("Do as I say, not as I do"??)
Oh, yea, and Magma annouced "gain-based" RTL synthesis this year, too, but
Magma also suffers from that damned missing customer tape problem.
"I attended the Get2Chip demo in their suite. I had suggested that
they focus on RTL rather than behavioral synthesis about a year ago,
and they have made that change. They have a new GUI which is simple
but usable.
They perform synthesis about 40x faster that Synopsys, but the main
attraction is that they perform automatic floorplan generation down to
the sub-block level. The concept is that top level wiring and buffer
management is the most important problem to work on, while the
sub-blocks are well managed by Cadence, Avanti, or Magma tools. I asked
about buffer chain insertion, and they are still working on that.
By setting a granularity level, larger or smaller sub-blocks can be
worked on. The tool generates a physical hierarchy based on the logical
one, and works to minimize the worst case path. It outputs DEF files,
and has the ability to manually place blocks (ie a CPU) as needed. They
do not do hard macros, preferring to optimize each instance. They have
the speed to do this (500k instances at 230MHz, 1.5um took 7 hours to
complete).
They do sophisticated optimizations to improve timing, tearing up
existing logic. At the architectural level, they do "value dancing"
ie moving MUXes after flops (Mealy state machines) to before the flops
(Moore state machines). This is something I have done by hand in the
past, but it is error-prone and time consuming. They also can replicate
logic cones which are heavily loaded, including replicating different
flavors of registers to divide the fanout.
I asked if this was done for physical optimization on the netlist, but
they were concerned that formal verification would break. I spoke to
Verplex about this, and they said it would be ok, as loing as they were
notified in the naming convention of the registers. So I asked Verplex
to talk to Get2Chip.
I think Get2Chip will have some market acceptance this year, their tool
is usable if a bit rough still."
- an anon design engineer
"It's a hard job for all the competitors of Synopsys, cause DC is the
standard. Whenever you are buying soft IP you get a DC script and if
you use your own script for another tool the IP vendor will no longer
guarantee for his code. For me the most interesting newcomer in RTL
synthesis was Magma, but they have the same problem and I'm not sure,
if their gain-base approach really works."
- an anon design engineer
"Get2chip looked really hot. Not only are they bucking for RTL status
they also have a firm grasp on what they call architectural synthesis,
or behavioral synthesis. I expect good things from them in the future.
Design Compiler looked like the same ho-hum synthesis tool it has always
been.
I was very dissappointed at the display and information given about
SystemC Compiler from Synopsys. I was expecting to see lots more from
this "SystemC" thing ("meaty" things not fluff that is)."
- an anon design engineer
"Nothing really new or worth switching from Synopsys. These other guys
are usually missing scan insertion/ATPG and who can afford to take a
chance on generating bad logic?"
- an anon design engineer
"Last year a group at my department evaluated the Cadence Ambit tool by
synthesizing one of our performance critical designs (a 160 k DSP core).
Prior to that we had done the same job with Synopsys DC, so we could
therefore compare the two netlists of the same design.
Because of the hype and the rumours about BuildGates at the time, I had
rather high expectations. But we were disappointed. We could not make
BuildGates produce a netlist that was as fast as, or faster, than the
one produced with Synopsys DC. Neither could the Ambit team themselves.
They sent over some guys to help us, and they sat with us for about
4 weeks, tried, failed, gave up and went home.
The greatest contribution from Ambit so far is their competition. In
98-99 Ambit forced Synopsys to increase the quality of results and the
execution speed of DC significantly. It was fun watching a challenger."
- an anon design engineer
"I attended the Synopsys Synthesis Road Map talk. The feedback they are
getting from their customers is that some ASIC sizes are now over 10M
gates in some cases and timing closure is definitely the biggest
problem. They went over all the added capabilities that everyone has
gotten in the past couple of years (have to justify that price somehow,
I guess) and put a lot of emphasis on ACS (Automated Chip Synthesis).
ACS allows someone with very little understanding of a design, like a
foundry, to do a reasonable job of synthesizing someone else's RTL.
They claimed that you get better timing with ACS than you do with
hand-generated constraints (quite a claim)."
- an anon engineer
"Design Compiler is still making its typical 10 to 15 % improvements a
year, nothing really impressive. Typical roadmap issues and promises
broken. I remember last year when we asked if the PrimeTime engine was
to be integrated into DC, answer: "Oh yes, we plan on it!" This time
around: "It would be an extraordinary task to have the same timing
engine in both tools and there are no short-term plans to integrate
them." In that same dying breath, this came out: "but we guarantee that
DC and PrimeTime to produce the same results and we are integrating all
the features absent from DC present in PrimeTime into DC." There were
many-o-audience members at DAC that had a conniption over that
statement. I interpret it as nothing but another brilliant revenue move
for the Great White Whale. Also, while I'm thinking of roadmap issues,
Synopsys did not deliver on the new DC GUI. Last year at New Orleans,
they presented the RTL Analyzer-like GUI as coming out in 2000. Instead
we see it is on the roadmap for this year (maybe next). What a joke.
My current perception of Synopsys DC is that they got kicked around by
the competitors and reacted and they are now back at the top and acting
like it. I tell you what, they are a really cocky bunch.
Sidebar here, but that cockiness is seen in their new pricing structure.
Synopsys knows their new perpetual pricing scheme forces you into the TBL
(Time Based Licensing) price structure, but at the same time tells you
that you are not forced to move into it. Yeah right! [ Company ] just
finished a TBL with them, which was nothing but a pain. Many times
during negotiations, Synopsys acted like our multimillion dollar
contract was not worth the effort. In the end, we finally got
everything straight. For others negotiating a Synopsys TBL, I have some
advice: watch out for KMPG. This is Synopsys' auditor, which almost
killed the contract on multiple occasions for revenue recognition
problems (you will hear that a bunch, too), but I diverge."
- an anon engineer
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