( DAC 00 Item 22 ) --------------------------------------------- [ 7/13/00 ]
Subject: Odd Birds -- Derivation Systems, Target Compiler Tech, InnoLogic
THREE ODD BIRDS: There were two formal tools at this year's DAC that sort
of defied categorization. One was Derivation Systems which offered DRS, an
odd sort of behavioral "synthesis" tool where you enter you design in the
form of either behavioral VHDL or their own proprietary language and then
you contunually partition and repartition the design till you're finally
down to "generic" gates. There are no timing constraints you give it and
it assumes you're making a fully synchronous single clock design. It's not
really a synthesis tool -- it's an architectural play tool -- all the
intermediate stages are fully executable. The idea is to use it to check
out one general design architecture versus another. One strange approach...
The second odd birds were the set of mostly DSP-specific architecture tools.
Talk about a limited sales potential! Exactly how many chip designers
are there exploring trade-offs between DSP architectures???
The last odd bird was InnoLogic "symbolic simulator" (and I'll let the
designers themselves tell you how that strange creature works...)
"Derivation Systems, Inc. sells a tool that uses a formal verification
method called derivation. For normal formal verification, you code up
your RTL, then you create a second description of your design and
compare the two. In this tool, you enter the desired function in a
LISP-like language, then partition it to lower and lower levels until
you reach RTL (or even gates for Xilinx or Actel). Partitioning is
controlled by the tool in such a way that the lower levels are
guaranteed to be equivalent to the original description."
- an anon engineer
"Derivation Systems - primarily a formal synthesis company, now has
LavaCORE JVM FPGA Core, a byte code uprocessor, another competitor."
- an anon engineer
"Target Compiler Tech sells a tool that has models for a variety of DSPs
written in their own language. You can compile C code and try running
it on several DSPs to see which one is best for your application."
- an anon engineer
"InnoLogic
- It is a symbolic Verilog simulator (e.g. "inputs are 'A' and 'B'
then the output is 'A+B'" compared to Verilog's "inputs are '1001'
and '0011 then the output is '1010'")
- Pretty cool stuff. Not limited to RTL and handles full Verilog
but only RTL can be symbollically simulated. You decide which
regs are assigned with a symbolic value and which one carries
regular literals. Symbols can also be used in expressions.
- You can get an exhaustive test with a single dataset but the size
of the simulation is the problem: currently only 50-500 kgates.
- If you could couple this with a Specman/Vera testbench to generate
the non-symbolic portions (the complexity grows exponentially so
you can't make everything a symbol), you'd have a killer
verification app. They are hip to the idea but it will require
changes in the HLV languages or the using user-defined primitives.
My only objection is it ties the testbench to the symbolic simulator.
How do you port it to a regular simulator who wants actual values
instead of symbols? You can't simply return a random value instead of a
symbol because you'll need to compare against an expected value that
also references the same symbolic value... Would keeping a list of
symbol/current-value pairs work??"
- Janick Bergeron of Qualis Design (VG 1.13)
"Functional Verification: InnoLogic Systems' ESP-XV. I saw a 2-hour
demonstration on their symbolic simulator before DAC. I think this
could be a great tool for increasing test coverage for functional
simulations and making test benches easier to write. They have
customers, too!"
- an anon engineer
"I believe you are talking about the ESP tool from Innologic that has
$esp_var and $esp_error. I haven't used 0-in personally, but I'd be
surprised if they were using the name of a competitors tool."
- David Madison of TransMeta (VG 1.13)
"0-in: great combination of formal verification and simulation
Real Intent: nice additional automatic check with 0 effort with some
nice features (FSM deadlock check)
Averant: full blown property checking: very nice for block level
control code verification
Innologic: ideal for datapath (symbolic verification)"
- an anon engineer
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