( DAC 00 Item 7 ) ---------------------------------------------- [ 7/13/00 ]
Subject: Cadence QuickTurn, IKOS, Thara, SimPOD, Axis, Simutech, Physim
BIG IRON STILL RULES: Although DAC is primarily a software show, one of the
big draws for those with large budgets are hardware emulators/accelerators.
One of the largest players in that field, Cadence's QuickTurn, didn't seem
to have that much to say at this year's DAC. But rivals IKOS and newbies
Thara, SimPod, and Axis more than made up for Quickturn's silence. And
oddly, the old hardware modeling group in Synopsys seems very, very quiet
this year, too. (Few mentioned them this year in their DAC reviews...)
"If you wanna verify analog parts with microprocessors and your HDL
design then use Aptix. If you wanna fast turn-around times use
QuickTurn. If you wanna a known user interface (applies for Modelsim
users) use Ikos."
- an anon engineer
"Ikos's transaction-level interface
- Works with CoWare's C-based environment but not limited to it
- Interface between testbench and design is at transaction level
(ATM cells, video frames, bus cycles) instead of pins/bit levels.
The lower frequency of data transfers improves runtime performance.
- Wish to standardize transaction-based API. There was an ST
sponsored meeting to promote the development of a standard
simulation to/from acceleration/emulation interface.
- How does that impact testbenches that must also work on
non-accelerated models? Must be able to replace calls to
HDL/Vera/Specman/C BFMs with transaction-based API calls.
- Design must be surrounded by emulated/accelerated bus model to
translate the transaction data into actual bus cycles.
Who will provide these models? Accelerators can handle behavioral
code but what if RTL code is required? IP-protection issues?"
- Janick Bergeron of Qualis Design (VG 1.13)
"Historically, Ikos has sold ASIC based hardware accelerators that
simulate with timing. Quickturn has sold FPGA based emulators that are
faster but do functional simulation only (no timing). Ikos and
Quickturn are now invading each other's territory. Ikos now sells an
FPGA based box that does functional verification only and an ASIC based
box that has timing but runs more slowly. Quickturn now has a
processor-based box, but it has no timing.
I got some Ikos lit that I'm not sure I understand. It sounds like you
can now interface with the box at a transaction level, rather than cycle
by cycle. The transaction is broken down into cycles on the box itself.
This allows the box to hum along without syncing up to the workstation
on every clock.
Simutech makes small accelerators that are resold by Quickturn.
Aptix sells boards that are sort of like an emulator, but you can plug
in actual parts as well. For example, if your ASIC is going to contain a
DSP core, you can buy an DSP part identical to the core, and emulate the
rest of your logic in the boards FPGAs. One box can emulate about 4M
gates (Quicturn has more capacity).
Axis sells an emulator box. It can emulate 10M gates plus has gobs of
RAM built in.
Dynalith sells iSAVE, a C language emulator for early algorithmic
verification before RTL is done. It is a very small box with most of
the C being done in a processor, and an FPGA to interface with the
outside world.
Physim sells a cheap board ($2500) that hooks a real part into a Verilog
simulation via PLI.
Tharas systems sells accelerators that use custom processors. They
currently do 2 state functional simulation, with 4 state coming. They
simulate 5K to 100K cycles per second."
- an anon engineer
"Tharas Systems 2 stars (out of 3 possible)
Hammer 50/32
Tharas makes a simulation accelerator box (Hammer 50/32) which works
with your simulator (currently VCS is supported with others to follow
including VHDL support by next year.) Most of the Verilog language
can be mapped into the acccelerator box leaving only a few items outside
that must run on the event-driven simulator running on the host
workstation. Even many non-synthesizable constructs sush as $display
or $monitor statements can be accelerated. The boxes are still somewhat
pricey $200K for a 4Meg gate system; $280K for an 8Meg gate box), but
the cost is better than other accelerator/emulator boxes. Two versions
are sold; one with the capacity for 4 million gates and the other
capable of handling upto 8 Million gates.
The box itself uses a special arrayed processor which is mapped into
handling the various logical tasks. Each box also contains a Gbyte of
memory for handling various memory arrays and registers. The advantage
of Thara is that it uses 3rd party simulators rather than their own
proprietary simulator."
- an anon engineer
"Axis Systems 2 stars (out of 3 possible)
Xtreme and Xcite 2000 H/W
Axis makes a suite of products in the hardware acceleration area and
their newest product Xtreme claims to combine simulation acceleration
with emulation within the same box. Xtreme can handle upto 20 million
gates, but beware of the cost for this capability. The older product
line (called Xcite) consisted of PCI-based cards which could plug into
your SUN workstation along with the necessary partitioning and control
software. The cards would provide a H/W accelerator for synthesizable
parts of your simulation environment.
Newer Xcite versions consist of a standalone box which allows one to
dynamically switch between running all events within the host computer
and moving as many events as possible to their special Re-Configurable
Computing (RCC) elements which provide the acceleration. In this mode,
the non-synthesizable constructs within the testbench remain in the
software simulator and are not handled by the hardware in the box. The
RCC's are synthesized into Altera FPGA's and are used to accelerate
the logic events. The logic is mapped into the RCC's according to an
RTL-level mapping and the simulator retains visibility to all signals
at the RTL level (not the gate level like many emulator boxes). A very
interesting capability that was shown in the demo was the ability to
start a simulation in S/W, switch to the accelerator box after the
initialization sequence, run until an error was found; switch back to
the software simulator, and dump waveforms for specific hierarchy
levels of events that occurred in the PAST without having to save the
entire state of the device to start with. I can't tell how many times
I wish I had had the capability to dump waveforms of critical events
after the timeframe of an error had passed. This capability is called
VCD-On-Demand and works in the simulation, acceleration, and emulation
modes. Target speeds for acceleration are around 10-100K cycles/second
and greater than 300K cycles/sec for emulation mode.
Drawbacks to this product are the reliance on their own version of an
event-driven Verilog simulator which they call Xsim. Some initial
ramp-up time is needed to map the DUT and testbench into these products.
This time could take anywhere from 1 to 10 days depending on the
complexity of the design and testbench. Changes to the design are
quicker thanks to an incremental compile capability. List costs for
these platforms range from an Xcite system for 1Meg gates at $300K;
a 2.5 Mgates Xcite box at $430K, and a 2.5 Mgates Xtreme box $600K."
- an anon engineer
"Oh, nothing world beating here. LogicVision looked good for Memory Bist
and maybe Logic Bist. Chrysalis works and will probably be here for a
while. You didn't mention Axis and they probably have the most
interesting accelerator/debugger at DAC."
- an anon engineer
"Our latest ASIC interfaces to multiple PowerPC microprocessors. In the
past we have used Verilog BFMs to verify our processor interfaces, but
this design is a multi-processor system and we needed a way to verify
the cache coherency. A BFM does not include a cache model or cache
snoop responses.
We chose to use the hardware modeling product from Simpod which uses
the silicon as a model. I'm not going to give all of the info, but
basically it allows us to use a chip just like any other BFM, giving
Verilog task calls like
$read(address, transfer_type);
and
$write(address, data, transfer_type);
from a Verilog testbench. Since it uses the silicon, it has the cache,
we can use it to verify snoop responses from the PowerPC. Besides the
ordinary $read and $write calls the model has a Verilog task interface
to set the state of a specific cache line in the PowerPC. This allows
us to do something like:
$cache_operation(address, state);
to set the cache line to an exclusive, invalid, or modified state. Then
our ASIC can do a bus transaction and we can see the snoop response of
the PowerPC. I don't want to get into a long discussion on cache
coherency, but Simpod gives us the model we need and we don't have to
spend time creating more complex BFMs for multiprocessor cache coherency
testing.
Simpod is an interesting new spin on the old concept of hardware
modeling. Using a hardware model like a BFM is nice because we don't
have to deal with any software the way you do with a full funtional
hardware model. The BFM testbench interface is all you need. I would
highly recommend it, with the following cautions. The company is very
small. They try hard, but if you don't have the bandwidth, things will
start to slip. We experienced delays in getting the hardware when it
was promised. If you understand the size of the company and that you
are dealing with hardware (like one of the engineers was moving the
Simpod system on his desk and the socket which holds the PowerPC broke)
it is a good way to go."
- an anon engineer
"We make extensive use of accelerator tools, mostly Quickturn/Cadence.
Quickturn had nothing new to tell me. IKOS' co-simulation environment
could be useful. The future will tell in our case. I was most
impressed with Axis this year. They make some claims that were
definitely impressive. We are definitely going to be looking into
this company and their acceleration tools."
- an anon engineer
"Biggest Lie? Axis Corp said they guarantee compiles in less than 1
hour. This is part of there demo suite presentation. When you dig a
little deeper you find out how they satisfy this guarantee. They use
a PC farm for their compile. It might only take one hour to compile
but you need 24 PC's for a 3-4 million gate design. Bigger designs
require more workstations if you're going to stay under an hour."
- an anon engineer
"Cadence/Quickturn didn't provide any information that we didn't already
know. I was hoping to hear more about Powersuite but that was not
mentioned. Cadence talked about Cobalt and Radium. We are currently
evaluating the Radium tool with the Powersuite software."
- an anon engineer
"Axis Corporation
This was definitely the most exciting presentation I saw. The Axis
Xcite 2000 should offer us Cobalt speed at one tenth the cost. They
also offer vcd on demand, which would do everything we hoped to get
from Powersuite. They recommend working with the Debussy tools,
which we are currently integrating into our simulation flow. This
tool should definitely help our productivity. Instead of running
simulations over and over for the correct traces we just run once. If
there is a failure the designer can debug from their desk. This was
the hope for powersuite but we have not seen that ability yet. All
things are not a perfect fit for our current simulation flow and this
tool. It would require some work to start using this tool. I think
we should certainly start looking into making this happen."
- an anon engineer
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