( DAC 00 Item 5 ) ---------------------------------------------- [ 7/13/00 ]
Subject: CAE Plus 'Afterburner'
BACKWARDS TALKING AM I: Talk about contrarians, while everyone's trying to
get from C/C++ to Verilog to gates, CAE Plus is trying to go *from* Verilog
back to *C*! The reasoning is that C models can execute 1000x faster than
Verilog models, so why not translate your Verilog to C? (Gee, I thought
that's what VCS and NC-Verilog did, no?)
"CAE Plus sells a tool that goes in the opposite direction. If you do
initial design in C and then start coding in RTL, their contention is
that once RTL coding begins, the original C model now falls behind,
making regression very hard. They have a graphical entry tool for
overall event flow (generates C and Verilog), then you do the detailed
Verilog RTL and use their other tool to translate it back to cycle
accurate C code."
- an anon engineer
"CAE Plus 3 stars (out of 3 possible)
Afterburner
CAE Plus makes a tool which takes Verilog code and converts it to a
C-language model. Suggested uses for this tool are for verification
acceleration (this is similar to a compiled code simulator such as
VCS or NC-Verilog) and also for IP delivery. They claim that it
provides a better simulation speedup than VCS. My more immediate
interest was in its ability to deliver IP in a non-Verilog source
code format. CAE plus also provides some related wrapper scripts
which generate a Verilog instantation model for use in a user's
testbench which can then call the C-language functional model. The
generated model is cycle accurate. The conversion is not exactly
pushbutton as it seems to require that any individual memory (SRAM or
DRAM, not register) be replaced by a "synthesizable model" which can
be handed by the conversion tool.
I found this tool worthy of further investigation due to its ability
to deliver IP. I think further investigation by our Applications
Engineering group might be prudent to discover if this tool can be
used to deliver simulation models of our various ASSP products (or
key simulation interfaces) without the need to deliver Verilog source
code. Since our customers are asking for such models & our competitors
are in many cases providing this capability, it is important for us to
come up with some method of delivering functional models to potential
customers for evaluation. This is especially important for [ product
deleted ] due to the multitude of operational modes and complexity.
- an anon engineer
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