( DAC 00 Item 3 ) ---------------------------------------------- [ 7/13/00 ]
Subject: Behavioral Compiler, Mentor Monet, Y Explorations, Frontier, Dasys
BAD BEHAVIOR: A few years ago, Synopsys did a big push in behavioral
synthesis, claiming that this is where designers would get the big 10X gains
in design productivity. They did their best to make it happen. Even Mentor
tried to ride that wave at DAC'98 with its Monet behavioral synthesis tool.
Summit (w/ Dasys) jumped in, too, along with Meropa. The only thing was
that the whole push towards behavioral synthesis simply never delivered on
its 10X promise, and, as a result, just never made it mainstream. Now
Synopsys BC has a small cult following. Nobody's using Dasys nor mentions
Mentor's Monet tools. Meropa almost went out of business, but switched
products mid stream and has become get2chip.com now. (C-Level tried some
behavioral, too, and got burned -- see the C-Level part of this report.)
Into this field of wounded jumps 'Y Explorations' from last year's DAC and
'Frontier', also from last year's DAC. A number of people burned here tend
to revert to using Synopsys Module Compiler to do their own datapath
synthesis and to use DC to make the control logic.
"Other vendors C-synthesis tools are less mature. For example, CynApps
synthesis ain't nothing but Dasys, which used to be a direct competitor
to BC under the guise of Summit. Dasys was much faster than BC, but had
some issues on single throughput designs. Also estimating delays from
the controller to the datapath had problems. Frontier Design's C
solution is another BC-like approach, but this time without any
estimating of gate delays. When I asked how you fixed timing problems,
the answer was changing your code/algorithm. Maybe (I hope) the guy
just misunderstood my question, but I don't think so.
It amazes me how CEOs will try to fit a square peg in a round hole to
generate revenue!"
- an anon engineer
"I enjoyed the Frontier Design demonstration from a Belgium company (a
spin-off of Mentor). They have Art Builder, which enables you to design
in C and generates a hierarchical Mealy state machine in VHDL or
Verilog. Art Builder gives the designer control over bit widths and
other data path resources.
They also have Art Designer for architectural synthesis. This is a fun
tool to explore architectures. After you write your code in C, you
specify the number and type of functional units the tool can use. It
shows you where your bottle neck is and then you can throw more hardware
at it or redo your algorithm."
- an anon engineer
"For C-Level the behavioral issues seem well thought out. Their idea to
translate behavioral C to DC makes sense. Synopsys is going from the
high-levels down; C-level is going bottom-up. Weird. I think they did
learn a lot from their BC experience. Frontier Design has a simular
tool to C-Level.
Last year for Frontier.
My understanding is that Mentor Graphics is welcome to join the SystemC
steering committee, but as usual can't decide what to do because they
don't have a clue on where the market it going. C-Level Design made it
clear that they will support SystemC."
- an anon engineer
"In the Synopsys suite itself, I was not impressed with Synopsys SystemC
synthesis flows. Basically it appears that Syonpsys has taken BC and
added a C reader to it. As I stated before, we evaluated BC and MC and
found BC to be severely lacking in single throughput designs. In fact,
anytime you had to pipeline the design you were asking for trouble. We
ended up with MC (Module Compiler), because we were able to get our core
stuff done with it. So, I thought it would be great of C plugged into
MC. When I asked questions about MC and other Synopsys tools, such as
Formality, working with C, the answer I got was comical: "We have no
idea, you need to approach MC/Formality/Vera guys and ask them, because
we do not know." Hmm, it seems that for a company pushing C as the next
great solution, they should have answers to this. Very disappointing."
- an anon engineer
"Y Explorations Inc. (yxi.com) has a tool that allows designers to code a
mix of behavioral code, RTL code and IP blocks. It goes before Synopsys
in the flow and provides the inputs for Synopsys to use. The designers
get a list of functions or procedures for which cores are available, and
can add their own functions. These are behavioral; they have no clock,
power-on reset, etc. You can have any number of versions of the same
function. If you have more than one, they graphically show trade-offs
between area, speed and pipeline stages to help you pick which version
you want. The really interesting thing is that they automatically build
a shell around your core to put it in its environment. They will vary
buffer sizing, add registers, and even modify state machines to allow a
core to be inserted. They also generate the Synopsys constraints for the
IP. The tool also understands that arrays in your code represent
memories, so it automatically creates the state machine to control the
memory when you put an array in your code. They say their tool is
superior to creating Synopsys DesignWare because it's easier to describe
a part, it accepts hard cores (cores where you are buying a layout) and
multi-cycle cores, and it does all the glue logic and modification of
state machines for you. They say it is superior to instantiating an
RTL model of your core because their model uses fewer pins (it's
behavioral), does the glue logic on it's own, modifies state machines
as needed and generates Synopsys constraints automatically.
My perception last year was that their success would be dependent on
getting lots of IP vendors to describe their cores with YXI's tool. So
far, they have been unsuccessful in that. The bulk of their customers
are in Japan and most of them are using it to describe their own design
blocks for internal reuse. I checked into describing blocks like
[ design name deleted ] within their tool. One problem is that all
clocks must have a fixed relationship to each other.
At the physical synthesis demos I asked both Synopsys and Cadence if
they have plans to do anything like this. In both cases a light bulb
lit up above the AE's head and they scribbled a note to themselves."
- an anon engineer
"yXplorations? "Y" as in "Why" have a blonde LA actress try to explain
how to get from high level C code down to gates? Now that is my
question... :-)"
- an anon engineer
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