( BSNUG 00 Item 13 ) ------------------------------------------ [ 10/13/00 ]
Subject: Design-For-Test (DFT), Scan, ATPG
BRAVE NEW WORLDS: One of the side issues in the Physical Synthesis battle
has been "How do we insert scan inside such a flow?". Synopsys R&D has
been working to expand their test offering with AutoFix, Boundry Scan
Compiler, and RTL Test DRC, and TetraMax. TetraMax has been very
enthusiastically adopted by customers, but it's primarily a frontend type
of tool. It'll be interesting to see it grow into the backend; and to see
how customers use or not use these other recent test enhancements, too.
If you want to understand the growing dominance Synopsys is getting in the
test world, just look at the Dataquest numbers. For 1998, Synopsys owned
94.4 percent of the test-chain-insertion market; Mentor owned 94.6 percent
of the ATPG market. For 1999, Dataquest reports that Synopsys owned 94.0
percent of the test-chain-insertion (no change); for ATPG, the new breakout
became 46.4 percent Synopsys and 45.6 percent Mentor (in one year Mentor
lost half of its ATPG marketshare to Synopsys!)
"FA2 - Design-for-Test and ATPG
This session was developed and given by Synopsys personnel, so it was
inherently biased, but overall was a good presentation of the
capabilities of the DFT Compiler and TetraMAX ATPG (automatic test
pattern generation) tools. Synopsys seems to have well integrated
DFT Compiler into their design flow after having initially purchased
it and premiered it as a stand alone tool. They have added an RTL
Test DRC (design rule checker) that is run early in the design cycle
to grade RTL code on it's potential testability. An AutoFix
capability allows the designer to let DFTC to automatically add
logic to the RTL code for added testability. That scares me a bit,
I wouldn't use that feature too often. Also added a Shadow Logic
DFT function which inserts MUXed-flop test points around designated
elements such as memories. Covered Boundry Scan Compiler (BSD) for
JTAG scan chain insertion, probably not applicable to us.
Finally, covered the TetraMAX tool. It, too, is well integrated into
the design flow. Seemed to run quite well and is straight forward.
The obvious downside is that you have to add a good portion of the
suggested scan for test logic in order to get good results with the
ATPG tool, but hey, that's what it's for, right? Issues: our standard
cell library will need to be modified for DFT and ATPG, I got the
name of the Synopsys weenie who handles this and she is shipping us
an ASIC library design kit that should tell us what we need to know.
Tidbits: ATPG tool supports pattern mapping (ex: we have fault pattern
for RAMs that we want followed) it will insert that into it's auto
generated patterns; supports pattern compression and sorting; has
multiple pattern generation algorithms so fast initial runs can be
made."
- Brian Fall of Microchip Technology, Inc.
"Design For Test (DFT) and ATPG
There are some very cool DFT enhancements in the 2000.05 tools
including RTL testability analysis, automatic fixing of certain DFT
violations, and automatic shadow logic for RAMs. The RTL checking
requires the Rest-RTL-Check license, which is included with DC-XP.
This feature will identify at the RT Level testability problems like:
o Uncontrollable clocks and asynchronous resets
o Latches enabled at the beginning of the test cycle
o Clock used as data
o Source register launch before destination register capture
o Registered clock gating circuitry
o Combinational feedback loops
o Multiple clocks feeding into Latches and Flops
o Black boxes
The idea is to give module level designers the ability to easily
identify and correct testability problems in the RTL, correct them
before any compile takes place, and avoid the most of the headaches
of debugging testability problems during full chip integration.
Autofix, when enabled, will automatically fix uncontrollable clocks
and asynchronous preset/clears. I have mixed feelings about this, as
I would prefer clean testable RTL. This would be very useful,
however, in the case of legacy designs in gate form with no access
to the RTL. This would have been very useful in a few previous lives.
The shadow logic feature will add "sink" registers for observability in
parallel to the address and data inputs of RAMs to capture any
combinational logic feeding into them. It will add "souce" registers
for controllability in parallel to the data outputs of the RAMs along
with a test_mode controlled MUX to drive any combinatorial logic after
the RAMs. It will also add logic to deal with the output enable and
drive the tristate nets on the output side of the RAM.
Another new feature is ScanPlanner. It provides a mechanism to write
out scan chain information in formats for Silicon Ensemble or Apollo,
and provides another mechanism to reorder the prelayout scan chains to
match the post layout reordered chains.
Coming soon is the ability to specify different clock periods for
mission mode and scan mode."
- Bob Wiegand of NxtWave
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