( ESNUG 399 Item 5 ) --------------------------------------------- [08/08/02]
Subject: ( ESNUG 398 #4 ) One User's Cadence Digital Mixed-Signal TSMC Flow
> I recently downloaded the TSMC 0.18 PDK and am trying to use it to prepare
> a layout for a IEEE-745 compliant floating point unit. I have the HDL
> written and simulated for it. I was recently introduced to the Cadence
> suite and would like to know a few things.
>
> 1. What is the preferred design flow if you are starting from a HDL?
> The flow that I am following was:
>
> ncvhdl - ncelab - ncsim (simulate the design) - BuildGates
> (for netlist ) - Abstract generator ( to generate
> LEF) - Silicon Ensemble for P&R.
>
> Is this the correct design flow?
>
> 2. I am trying to create a tech.dpux file using the tsmc18 techfile.
> I give the library name and the cds.lib file properly. But when I
> start up cds2hld_4.4 it gives me an error saying it cannot read the
> default.drf file. I want the tool to read the display.drf file
> provided by tsmc which is in my current working directory. What env
> variables should be set for this?
>
> 3. Is there any other method of creating a tech.dpux file and also to
> create a LEF?
>
> Any help is greatly appreciated.
>
> - Shrirang Yardi
From: [ Cadence-a-saurus ]
> 1. What is the preferred design flow if you are starting from HDL?
My quick digital mixed-signal 12-step nanometer flow:
1. Write your RTL (add Verliog-A/Verilog-AMS for the SOC while
you're at it).
2. Functionally verify using AMS Designer (NC-Sim & Spectre) or
just NC-Sim.
3. Build your RF, Analog, & Mixed-Signal blocks (VXL, VCP, VCR,
NeoCell, etc.)
4. Create LEF for your RF, Analog, & Mixed-Signal blocks using
IC50 'abstract'.
5. Create TLF for your RF, Analog, & Mixed-Signal blocks using
MDL & Ocean.
6. Synthesize the digital portions of your design using PKS.
7. Prototype using SOC Encounter.
8. Route using Silicon Ensemble.
9. Extract using Fire & ICE QXC & use CeltIC for crosstalk analysis.
10. Sign-off delay & timing in PKS (#6 thru #10 are integral to
SOC Encounter).
11. Assura DRC & LVS & critical-path extraction/simulation via
Assura/Spectre.
12. Chip Finishing back in the famous DFII (IC50) cockpit.
My team has taken an RF/Analog/Mixed-Signal/digital/Digital design thru
this (and other) flows, using all latest released tools, and aiming for
zero lines of workaround code; then documenting every single button
press -- and passing the results to the QA folks to begin to ensure
these basic flows continue to work, from release to release.
> 3. Is there any other method of creating a tech.dpux file and also to
> create a LEF?
a. I've done it a few times on our generic IC baseline design
(containing RF, Analog, Mixed-Signal, digital, and Digital blocks).
b. If you have a standard-cell library, e.g., from Artisan, the _easiest_
way (by far) to create a tech.dpux file (do you _really_ want that as
the end goal?) is simply to start the 'abstract' program and import
the Artisan supplied TSMC technology LEF & save the results to the
tech.dpux file.
c. To spit out LEF, you can use that same 'abstract' GUI which allows you
to tweak the parameters (e.g., antenna information, pin information,
rectilinear boundaries, routing info, keep outs, etc.) as desired.
See you at ICU in September!
- [ Cadence-a-saurus ]
---- ---- ---- ---- ---- ---- ----
From: Shrirang Yardi <syardi@hotmail.com>
Thanks a million for the 12-step nanometer flow. :) My question was:
- I don't have TSMC technology LEF but just the TSMC technology file.
does MOSIS provide the LEF too? I have just the TSMC "techfile" to
start with. I wanted to know a step-by-step procedure for converting
this techfile to a tech.dpux file so that I can feed it to abstract.
Am I correct in this or have I missed something?
- You mentioned that you have written a step-by-step guide. Is it possible
to obtain this guide from the MOSIS web-site as I am an accnt holder
at MOSIS?
Please do let me know. Thanks a lot for your help.
- Shrirang Yardi
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