( ESNUG 398 Item 9 ) --------------------------------------------- [07/31/02]
Subject: ( ESNUG 396 #4 ) Synopsys Slow Getting Floorplan Compiler To Users
> Floorplan Compiler (v2002.05) is available at the SNPS ftp site. Does
> anyone know if Chip Architect licenses will be converted to FPC licences?
> I'm meeting with my SNPS folks today to ask that question, but would like
> to double check this. With tight budgets and the risk of more layoffs,
> now is not a good time for me to suggest the firm even evaluate another
> tool. But since we already have two Chip Arch licenses...
>
> - Mark Wroblewski
> Cirrus Logic Broomfield, CO
From: Mark Wroblewski <markwrob@colorado.cirrus.com>
Hi John,
FWIW, Synopsys has been dragging their heels with me about getting an FPC
eval license. It has been more than two weeks since I requested it. I
believe this indicates that in spite of the announcement of the tool's
availability, it is really available only to a select few customers while
the big kinks are still getting worked out. I'd be surprised if more
than 2 or 3 designs tape out using FPC in the next 6 months.
FWIW #2, I found out from my Synopsys sales guy that Chip Architect comes
in two flavors, an entry-level version and a more powerful suite. I think
the latter is labelled CA-Expert or maybe CA-Ultra. Anyway, the sales guy
stated there is reasonable room to talk about converting the more powerful
Chip Architect suite to an FPC license, but you can't expect a direct
conversion of the entry-level Chip Architect tool to an FPC license,
generally speaking. That shouldn't keep people from asking about any such
deal when the right time comes, as nearly every customer's account status
with Synopsys can differ.
For the time being, we've still got two Chip Architect licenses my firm
picked up this year, that no one uses as far as I know, and we have no
ability to even try FPC yet. It would have been nice to get the eval out of
the way this month, but now it's probably getting too late to eval any tool
before getting dirty on our next tapeout, so we'll probably stick with the
Cadence SE/CTGen/Design Planner approach from last chip, as painful as it
may be.
- Mark Wroblewski
Cirrus Logic Broomfield, CO
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