( ESNUG 398 Item 6 ) --------------------------------------------- [07/31/02]
From: Gnana Kanagaratnam <gnana@mondes.com>
Subject: How Monterey Aristo IC Wizard Estimates Initial SoC Area Budgets
Hi John,
I'm an applications engineer supporting IC Wizard at Monterey. Over the
past year, I've received a lot of questions about how IC Wizard calculates
initial area budgets for SOC designs. In designs dominated by standard
cells, this is very straightforward -- just sum up the total cell area and
multiply by your favorite utilization factor. However, this approach does
not work well in designs dominated by hard blocks. IC Wizard allows you
specify different utilization values for standard cells & hard blocks.
The user defines standard cell utilization and hard macro utilization with
the following commands:
set context -blockset <design_name> -version <version_number>
run updateBlockSize -standardcellutil 80 -hardblockutil 90
In this example, IC Wizard will calculate the total area occupied by
standard cells and then add extra area such that the utilization equals 80%.
Similarly, it will sum up the total area occupied by hard blocks and add
extra area such that the utilization is 90%. For designs that contain both
standard cells and hard blocks, both utilization values are used to
calculate the total area of the design.
For designs containing multiple levels of hierarchy, IC Wizard will traverse
the hierarchy down to the lowest level, then apply these utilization values
and calculate a bottom-up area estimate for the hierarchical block at the
top level. Standard cells and hard blocks have library attributes that
IC Wizard uses to determine which utilization value to apply. Standard
cells are of class CORE and hard blocks are of class RING, BLOCK, COVER,
or ENDCAP.
Standard cell utilization value is affected by your synthesis methodology.
If you use conservative timing models, then the initial area estimates out
of DC will be (more) pessimistic, thus the cell utilization factor can be
more aggressive. Conversely with an optimistic timing model, you should use
more conservative cell utilization.
Coming up with good default hard macro utilization is a little tricky. This
is affected by many factors including, does the design contain many dual
ported memories, how neatly the hard blocks tile, pin density, do the blocks
vary in size dramatically.
- Gnana Kanagaratnam
Monterey Design Systems Sunnyvale, CA
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