( ESNUG 394 Item 9 ) --------------------------------------------- [05/29/02]
Subject: ( ESNUG 393 #12 ) How To Handle Hard & Soft Macros In Cadence PKS
> Yup, I get black box warnings (when I don't read in a Verilog shell).
> So PKS will not be happy until it gets a tlf or alf? I guess that's the
> problem. I've been trying to get away without doing that. I was hoping
> that it would intuit the info from a DEF and/or Verilog shell.
>
> - Albert Ma
> MIT Cambridge, MA
From: Glenn Gullikson <glenng@cadence.com>
Hi, John,
There are several ways to handle custom blocks within PKS -- either as soft
blocks or hard blocks. The hard block approach requires a physical model
(LEF) and timing model (TLF or ALF). Without the timing model, the hard
block will have no timing associated with it. If you access to PKS 5.0,
then the easiest thing to do is to use the do_extract_timing_model command
to generate a TLF. This can generate either a black box or grey box model
depending on what you are looking for. This is done by loading, at minimum,
the Verilog for the block and the timing constraints:
<load libraries>
read_verilog <verilog_file>
do_build_generic
source <constraints_files>
do_extract_model [-black_box] -cell_name <block_name>_model \
<block_name>.tlf
This will generate a timing model based on the available timing which is the
WLM from the library in this case. For more accurate timing, then load
either a placement (Steiner based timing), SPEF (annotated parasitics), or
SDF (annotated delays). The model will be generated for whatever timing is
loaded at the time.
Regarding the "physical information not found" message. That is happening
because there is no "cell" to bind the LEF to. LEFs are either for
"physical only" cells (instantiated in the DEF and not the Verilog) like
fillers, dcaps, etc. or for instances with timing models associated with
them.
With PKS 5.0, there is another way to deal with this situation and this is
through the creation of soft blocks. A soft block is an instance in the
design that does not have a timing model but has a physical hierarchy
associated with it. This is applicable in Albert Ma's case.
The way to handle this is:
<load libraries>
<load top level verilog design>
<load floorplan information>
read_verilog <verilog_for_the_datapath_block>
create_physical_cluster -name <cluster_name> \
-bbox <cluster_bounding_box> \
-location <cluster_location> \
-instance <logical_instance>
At this point, you can push into the cluster and load placement information
or SPEF/SDF information as discussed previously:
do_push -cluster <cluster_name>
[ read_def <cluster_placement> | read_spef <spef_file>
| read_sdf <sdf_file> ]
do_pull
At this point the design can be optimized and will use the timing for the
soft block during optimization and stitch that timing with the timing at the
top level. The contents of the soft block will not be touched and the top
level placement will in essence treat it like a hard block but since the
contents of the soft block are "visible" the top level optimization will be
able to see the drivers and loads in each of the soft blocks for accurate
incremental timing.
- Glenn Gullikson
Cadence San Jose, CA
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