( ESNUG 392 Item 7 ) --------------------------------------------- [04/18/02]
Subject: Synopsys R&D Q&A To The SNUG'02 PhysOpt Tutorial
1. Which version of Physical Compiler will work with ClockTree
Compiler and Route Compiler? When will they be available?
ClockTree Compiler and Route Compiler are in Beta now. When they are
available, they will interact with Physical Compiler.
2. Will Physical Compiler change ports at a lower-level hierarchy
during optimization? For example, a reset signal.
Yes, it allows boundary optimization, but only in the
RTL-to-placed-gates flow.
3. What is the sweet spot for the number of gates in
gates-to-placed-gates and RTL-to-placed-gates?
The sweet spot is 400K instances or less for gates-to-placed-gates and
300K gates for RTL-to-placed-gates.
4. (Slide 51) Can you make set_delay_estimation_options pessimistic to
help routing?
Yes, the command is there to help you influence the delay calculation
used in placement and routing estimation, allowing you to override
values derived by Physical Compiler. However, you might not want to
make it too pessimistic as it can have significant runtime impact.
5. (Slide 49) Why is set_load file required when you have SDF for
post-route incremental optimization?
The capacitive loads are required for design rule fixing.
6. How is the Physical Compiler flow different from the Floorplan
Manager flow? Is this going to obsolete the reoptimize_design
function?
The Physical Compiler flow takes more physical information and the
results are more accurate. The tool demand is market driven. There are
still many customers using Floorplan Manager and enjoying great
success with this product. Floorplan Manager will be supported into
the future.
7. What is the runtime comparison between Physical Compiler and Design
Compiler for noncongested designs?
For noncongested designs, typical Physical Compiler runtime is about
1.5 times that of Design Compiler. It also varies with tighter or
looser constraints.
8. Is there going to be a more automated RC correlation flow?
The current RC correlation flow is as automated as you can get with
the current environment. It can be further automated only when we have
detailed router and RC extraction tools integrated.
9. Can you explain what RC correlation is?
RC correlation flow is the process of comparing RC parameters before
and after routing, and then tuning RC parameter values to reflect the
true wire delay values.
10. Will Physical Compiler be able to read SPEF?
Yes, Physical Compiler will be able to read SPEF. However, Physical
Compiler uses Elmore as its delay calculation algorithm. The algorithm
is very fast but can produce more pessimistic results. The current
recommended flow is to read SDF and set_load files generated by your
preferred extraction tool for back-annotation.
11. How do you handle I/O placement?
I/O placement is done in a floorplanner such as Chip Architect.
12. Is there any plan to support ACS in Physical Compiler?
No, there is no plan to support ACS in Physical Compiler.
13. (Slide 20) What kind of timing information does PrimeTime use from
Physical Compiler at the post-route stage? Is this a pure design.db
or does it have parasitic information?
At the post-route stage, PrimeTime needs a design.db generated by
Physical Compiler and some parasitic information (SPEF/DSPF/rSPF)
produced by a routing tool. For pre-route stage, PrimeTime can read
the post Physical Compiler design.db and time your design with no
further information being required. The results from PrimeTime will
match the results from DesignTime (in psyn_shell).
14. (Slide-20) If you don't use wireload models, what do you use for
the first netlist?
In this slide, we are showing the RTL-to-placed-gates flow. The first
netlist we will produce is by using Design Compiler. If you have
wireload models in your technology library, they are used. Otherwise,
it is OK too. The purpose of generating the first netlist is for
floorplanning. A floorplan is required for the Physical Compiler flow.
At compile_physical stage, no wireload model is required.
15. (Slide 20) Is the netlist after compile a Gtech or mapped?
The netlist is mapped to the target library.
16. (Slide 46) What are the inputs to an ECO flow?
The inputs are a new netlist and the old placement file.
17. What options can I try to minimize changes for physopt -inc
-post_route?
You can use the -effort low and -size_only options to minimize
changes.
18. Does it produce a change list file after physopt -incremental?
Yes. You have to set the variable 'physopt_change_list' to true (the
default) before running incremental physopt. After the incremental
run, you can use the command 'report_change_list' to report the
changes.
19. Why do you need to be pessimistic in constraints for Design
Compiler and realistic in constraints Physical Compiler?
The reason is simple: Design Compiler uses wireload models and they
are statistical and inaccurate. The pessimism added to the constraints
is to allow some margin for the backend tools. Similarly, concurrent
placement and synthesis in Physical Compiler accounts for the wire
delays quite accurately already. There is no need to be pessimistic.
20. Do you have to have a floorplan .pdef file to go into Physical
Compiler? Can you do it in Physical Compiler itself? Are there
sufficient commands in Physical Compiler to do the floorplanning
in Physical Compiler?
Yes, you do need to have a floorplan for Physical Compiler, whether
input from some PDEF file generated by other tool or created by
Physical Compiler floorplanning commands. Physical Compiler does have
sufficient commands to create necessary floorplan objects.
21. In a hierarchical Physical Compiler flow, some blocks are multiply
instantiated. How is the optimization handled?
The logical hierarchy in Physical Compiler is maintained throughout
the optimization. Physical Compiler handles the physical hierarchy of
the design as a flat entity. There will be no conflict in the logical
hierarchy and the physical hierarchy.
22. Routing on different metal layer gives different RC. Does Physical
Compiler take into account the different metal layers during
optimization?
Yes, it does.
23. Can Physical Compiler replace Design Compiler and Floorplan
Manager?
You can look at it this way: Physical Compiler is a superset of Design
Compiler and processes more detailed information than Floorplan
Manager.
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