( ESNUG 390 Item 2 ) --------------------------------------------- [03/20/02]
Subject: ( ESNUG 388 #8 ) Cadence CTGEN & CT-PKS Easily Meet This Skew Goal
> I'm wondering if anyone in ESNUG has experience working with Cadence's
> CTGEN (clock tree synthesis tool) in Silicon Ensemble.
>
> I have a design with complexity of about 500 K gates, 0.25 um technology.
> The largest clock domain (100 MHz) has around 9,000 flip-flops connected
> to it, and clock skew requirement for that domain is 0.25 ns (this number
> was obtained from post-synthesis STA. Does anyone know if such a skew
> requirement is achievable by CTGEN?
>
> - Suttinan Chattong
> Centre For Wireless Communications Singapore
From: Satya Sridhar <satya.sridhar@wipro.com>
Hi, John,
In one of our designs, we could achieve a skew of 0.28 nsec using CT-PKS for
a 500 Kgate design with 9,121 flops. That skew value is from the clock tree
report from PKS.
- Satya Sridhar
Wipro Technologies Bangalore, India
---- ---- ---- ---- ---- ---- ----
From: Arvind Raghavan <arvindr@vitesse.com>
Hi, John,
We ran a design through CTGEN that has about 20,000 flops and we were able
to get a skew of about 750 psec. This was in 0.18 um design, so I think
you should be able to meet your skew requirements. Please note that CTGEN
allows you a lot of flexibility and you might have to run CTGEN a couple
of times to get the optimal skew. CTGEN uses a constraints file which
contains a structure for the clock tree. You can manipulate this to get
the optimal tree you want.
- Arvind Raghavan
Vitesse Semiconductor Camarillo, CA
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