( ESNUG 387 Item 12 ) -------------------------------------------- [01/23/02]
From: "Mathias Kohlenz" <mathias_news@kohlenz.com>
Subject: Seeking A Code Coverage Tool That Covers Schematic Entry Blocks
I'm currently looking for a code coverage tool which is able to handle
blocks designed with schematic entry. This is probably not possible for
the schematic design itself, however for the synthesized design it should
show which gates were driven. So far, we used "Nccov" which came with
the latest release of the Cadence NC-Verilog simulator, however it neither
handles primitive instantiations nor "assign" statements.
- Mathias Kohlenz
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