( ESNUG 385 Item 15 ) -------------------------------------------- [12/19/01]
From: "Pradip Thaker" <pthaker@zagrosnetworks.com>
Subject: How Do I Best Fill The Holes In A Cadence PKS/BuildGates/SE Flow?
Hi, John,
We use Cadence PKS for our synthesis and back-end needs. However, we are
currently looking to fill up the tool gaps such as DFT needs (JTAG, RAMBIST,
DFT Checker, ATPG, etc.), formal verification, etc.
I am familiar with some choices (especially the ones that fit well with a
Synopsys-based flow such as TetraMax, Formality, etc.) You can also add
Static Timing Analysis (Perl v/s Primetime) issues to this list. I am also
familiar with other solutions such as Verplex, FormalPro, FastScan, GenSys,
SynTest, LogicVision products, etc.
So many permutations are possible. My question is what fits really well with
Cadence Cadence-PKS/BuildGates/SE flow, what are the issues?, what works?,
what doesn't work well?
- Pradip Thaker
Zagros Networks Rockville, MD
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