( ESNUG 385 Item 10 ) -------------------------------------------- [12/19/01]

Subject: ( ESNUG 383 #1 ) I'd Like To Hear More About Ambit-RTL's Bad Logic

> 3) Bad logic from Ambit BuildGates.  Yes, Ambit-RTL produced bad logic
>    in our case.  We caught the bugs in Verplex.  The problem did not
>    stop us from using Ambit because DC is too slow and area consuming.
>    It's a trade-off.  We can handle the bug instead of delaying the
>    chip and getting larger area.
>
>     - Ching Hsiang Yang
>       Sunplus Technology                         HsinChu, Taiwan


From: "Mark Warren" <mwarren@xtremespectrum.com>

Hi, John,

I'm a PKS user, too.  Ching, can you expand on the problems you saw with
the logic?

    - Mark Warren
      XtremeSpectrum


 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)