( ESNUG 385 Item 3 ) --------------------------------------------- [12/19/01]
From: "Kathleen Meade" <meade@cadence.com>
Subject: Tips For Getting High Speed Sim With Cadence NC-Verilog & NC-Sim
Hello John,
I'm sending this to give your NC-Verilog and NC-Sim readers a summary of
command-line options and how they affect simulator performance. It may give
them some hints as to how to maximize NC-Sim's performance for their designs
and testbenches. I will show the syntax of command line options as they
apply to the single-step invocation mode (ncverilog +<options>) and indicate
the alternate ncvlog/ncelab/ncsim options in parenthesis.
My first tip is this: Please try to use the latest release of Cadence LDV
software that is available. Ever since NC-Verilog was first released (in
1996) our R&D team has focused on simulator performance as a highest
priority requirement. In every release they continue to add enhancements
that optimize the simulator for specific design styles, so always try to use
the latest. As of this date (12/07/2001), the latest release is LDV3.3(s10).
My second tip is similar: Use the profiler built into the NC products. The
profiler generates a log file listing which modules, lines of code and
construct types are taking the most time in the simulator.
+ncprofile (ncsim -profile)
By default, if timing exists in your design, NC-Sim will run with full
timing, sdf annotation and timing checks. There are options available to
reduce the timing capability, speed up performance and reduce the design
size. A quick command line string to use for max performance when you're
not concerned with timing is:
+delay_mode_distributed +notimingcheck +noneg_tchk
Here are some other global timing options:
+no_notifier (ncelab -nonotifier) :disables notifier register
+notimingcheck (ncelab -notimingchecks) :disables timing checks
+delay_mode_unit (ncelab -delay_mode unit) :delay 1 sim time unit
+delay_mode_zero (ncelab -delay_mode zero) :zero delay
+delay_mode_distributed (ncelab -delay_mode distributed)
:ignores specify block delays
We have also recently (LDV3.3) added the capability of applying timing
options to specific modules in the design using a timing control file. You
can enable/disable timingchecks, iopath delays, port delays, primitive
delays and full timing on a module by module basis. The syntax of the
control file is described in cdsdoc.
+nctfile <timing_ctrl_file> (ncelab -tfile <timing_ctrl_file>)
SDF precision can also be controlled. Previous to the LDV3.1 release the
default SDF precision was truncated to 10ps. As of LDV 3.1, all timing
values (including those less than 10ps) are used. This results in more
accurate results but slower simulation. (In most cases, 10 ps is
sufficient).
+ncelabargs+"-sdf_precision 10ps" (ncelab -sdf_precision [10ps|1ps|100fs])
Special Note on Negative Timing Checks: In the LDV3.3 release (July 2001)
we changed the default behavior of the simulator on negative timing checks.
The new behavior is if a negative timing check exists, it WILL be used.
+neg_tchk (ncelab -neg_tchk) : still exists for backward compatibility
+noneg_tchk (ncelab -noneg_tchk) : to set negative timing checks to zero
Previous to the LDV3.3 release, you must specify +neg_tchk
(ncelab -neg_tchk) on the command line for negative timing checks to be
applied.
Now for some switches that might slow down performance but are useful for
debug. By default, the NC products run in a fast mode with minimal
debugging capability. To access signals, modules and lines of code during
simulation, debug options can be applied using the access and linedebug
options.
+access+[rwc] (ncelab -access r|w|c)
r : read capability for waveform dumping
w : write for modifying values through PLI or TCL
c : connectivity for querying drivers and loads in C or TCL
+afile <access_file> (ncelab -afile <access_file>)
:to specify access options for specific modules in the design.
+linedebug (ncvlog -linedebug)
:to set breakpoints on lines of code during simulation
This causes more of a slowdown than the "access" options
I hope that this information proves useful to the ESNUG readers.
- Kathleen Meade
Cadence Design Systems Atlanta, GA
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