( ESNUG 381 Item 13 ) ------------------------------------------- [11/08/01]
Subject: ( ESNUG 380 #13 ) I Found A Laborious Way To Handle Resets In DC
> ... meant for each block being synthesized there were effectively 2 reset
> trees, one with an invertor as its driver. Consequently it was not
> possible to simply apply the "set_ideal_net" type commands and expect DC
> to not put buffers in the inverted reset tree, as the invertor protected
> the inverted-tree from such constraints. ... In the end it WAS possible
> with some fiddling around using commands like clean_buffer_tree to strip
> out all reset buffers, but I still had the problem that mylayout tool had
> to cope with a few dozen invertors midway down the reset network. ...
>
> - Jon Harris
> Siroyan Reading, Berkshire, UK
From: Jon Harris <jharris@siroyan.com>
John, I know you like follow ups. I did find something on SolvNet which
would help with this issue, but is very laborious. Essentially you label
*every* sequential 'always' block in your source code(!), create hierarchy
around these in DC, synthesize these to the appropriate flop & reset logic
and set_dont_touch.
Needless to say I haven't gone down this route!
- Jon Harris
Siroyan Reading, Berkshire, UK
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