( ESNUG 379 Item 15 ) ------------------------------------------- [10/11/01]

Subject: ( ESNUG 376 #11 ) The Specman Side Of The Vera/Specman Debate

> I am experienced with are Specman and Vera.  Majority of the people I am
> familiar with are using Vera and some are using Specman.  I don't know
> anyone using Rave.
>
>     - Faisal Haque
>       Cisco Systems


From: Yossi Levhari <yossi@veri-sure.com>

Hi John,

I want to add a little more to the Specman/Vera debates.  I am wondering if
people can see:

  1) How much revenue Vera is claiming within deals including (VCS, Design
     Compiler, wave viewers, VCS)?  The advantage Verisity has is if they
     say they sold in $1, you know what they sold.  For example, I wonder
     has any Synopsys client bought just Vera with a MTI simulator?

  2) I would like to see a clear message from Synopsys about what SystemC
     is and what Vera is and how they connect.  (A year ago this was not
     clear.)

I would like to add a ('Specman biased') opinion to counter Faisal Haque's
'VERA biased' ones that he expressed in ESNUG 376 #11.


>  1) Performance.  I give Vera the edge here.  Specman does not work with
>     Save/Restore in VCS.  But both tools need to improve in this area.

Specman works very nicely with save and restore in VCS.  It also allows just
saving one side (Specman, or RTL) side.  Even when I worked in Verilog, it
always stays around 10-30% overhead on the testbench side so even if the
verification is improved 10x it still will only improve overall performance
by 20%.


>  2) Ease of Learning.  Definitely give a huge edge to Vera.  Whereas Vera
>     is very similar to traditional languages such as C++ and Verilog,
>     Specman has its own unique, non-intuitive lexicon.  This I think is
>     its biggest weakness.  Learning curve for Vera is in weeks whereas
>     learning curve for Specman is in months.  Feature wise they are both
>     powerful and very comparable.

It seems that this is the most major point being made here, and I would
guess that Faisal's first language is VERA (of the two that is).  In general
terms Vera is more 'verilogish'.  It is not like C++ unless constructors is
considered C++.  I would make a statement that an engineer coming from a
solid 'software engineering background' will see Specman as easier where the
opposite (EE background) will see Vera as easier.


>  3) Support for Concurency .  Give Vera an edge here, too.  It has more
>     built-in concurrency constructs which are more generic and therefore
>     more widely applicable.

Specman has 'fork/join' (called "all off", "first off")


>  4) Test case generation efficiency.  Specman gets the edge here because
>     of its more powerful recursive constraint solver.

Actually even here this is not true.  The constraint solver works its way
recursively on the verification hierarchy, but for each item it generates it
does it 'correct by construction' (somehow recursively I hear backtracking.)


>  5) Testbench creation efficiency.  Vera gets an edge here.  This is due to
>     longer debug cycles, because of the non-intuitive nature of Specman.

Specman has a very powerfull debugger + wave form support.  (I do not know
this about VERA.)  The Specman debugger has the ability to debug parallel
threads together, having break points on both code, and data events.


>  6) Temporal expressions.  They appear to be even.  Vera has recently added
>     support for temporal expressions.  However, Vera's syntax appears to be
>     more intuitive.

Be serious !!!  How can you compare Vera's Temporal?  Have you used it ?


>  8) Code Reuse.  Vera has the edge here because of the virutalized RTL
>     interface capabilities, also the more structured object oriented
>     paradigm is easier to maintain in a large collaborative environment.

Code reuse is not a function of a language.  It is a direct outcome of your
architecture.  So I do not see how this statement can hold without
collaborating data.  How many projects have you taped-out using Specman, and
how many VERA ?

And what about:

  Coverage ?
  FSM coverage ?
  synchronization events ?
  VHDL ?  mixed VHDL-VERILOG models ?
  Verification Advisor ?
  Models ?
  IP ?
  Support ? (questions etc ...).

Also, I would like to know how many of the original System Science R&D have
stayed aboard at SNPS as their product seems very 'stable'.  (No new
features, that is.)  Verisity is very rapidly pursuing new frontiers
(coverage maximizer/formal demos etc ....).

    - Yossi Levhari
      VeriSure Consulting Ltd.                   Zichron Yaacov, Israel


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