( ESNUG 379 Item 8 ) -------------------------------------------- [10/11/01]
Subject: ( ESNUG 378 #10 ) Analog Simulator With PrimeTime For PCI Specs?
> One approach is to constrain the delay using the set output delay and use
> some arbitrary load capacitance. Then using PrimeTime to generate a
> timing report for the clock-to-output paths. From the timing
> report determine the delay up to the input of the PCI output buffer. To
> determine the delay associated with the buffer use an analog simulator
> tool like Interconnectix and IBIS models simulate the driver and the
> backplane. Add this delay to the internal delay from the PrimeTime
> report to get the total delay.
>
> Is this good appoach or is there a way to do this only using PrimeTime?
>
> - Lou Villarosa, Jr.
> Honeywell Space Systems Clearwater, FL
From: "Hui Fu" <Hui.Fu@infineon.com>
Hi John,
I think the PCI spec has the load information for 3.3v signal timing.
(rev2.2, pg 123 and pg 128). For maximum timing, the condition is 10 pf
with 25 ohm pull down/up for rising/falling edge. For minimum timing,
the load is 10 pF with 1 K ohm pull up and pull down. However the V/I
curve requirement for the driver has to be respected also. But that
should already take into account during your I/O cell (pad) design.
Extensive analog simulation should be already performed during the I/O
cell design.
To be able to use PrimeTime for delay calculation, the resistor effect
need to be considered in your library characterization. The values given
in the .lib or your STAMP model are simulated with the specified
resistance( 1 K for min, 25 for max). So you only need specify the pad
load (10 pF) to get the right delay of the pad cell. However if the
library has not take those into account, you can not avoid to use the
analog simulator along with PrimeTime.
- Hui Fu
Infineon Asia Pacific
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