( ESNUG 379 Item 5 ) -------------------------------------------- [10/11/01]
Subject: ( ESNUG 378 #4 ) Equivalency Checking Finds Yet Another Presto Bug
> A couple of months ago I discovered that Presto (DC's new HDL Compiler)
> doesn't have all the kinks worked out. Our team decided to use Presto's
> support for new Verilog features in our RTL code. ... Seems as though
> Presto is bug ridden. The Synopsys support engineer conveyed that much
> to me through my email exchanges with them.
From: Theo Band <tband@lucent.com>
Hi John,
I used Presto to speed up reading a Verilog netlist. The result was that
the netlist was broken because some bussed port got swapped. (2000.11-SP1)
I submitted the following bug report to Synopsys, Inc.:
module latchin ( din, min, cin, ti, te, .dout({dout_15_3, dout_15_2,
dout_15_1, .....})
After instantiation of the above module the connections to the "dout" bus
are swapped. Using the old netlist reader by setting
enable_verilog_netlist_reader = false
solves the problem. The problem was discovered by equivalency checking
close to tapeout. Since we do only PrimeTime verification and hardly any
functional verification on this netlist, I consider this a major bug.
Please inform your other customers about this error as soon as you're
able to recreate it.
The problem was identified and STAR 122936 has been filed. I cannot find
this STAR on SolvNet however. So be warned if you have these constructs in
your netlist while using Presto.
- Theo Band
Lucent Technologies Huizen, the Netherlands
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