( ESNUG 379 Item 4 ) -------------------------------------------- [10/11/01]
Subject: ( ESNUG 378 #2 ) Turning Off The Secret "Consume Licenses" Switch
> Synopsys seems to grab a VHDL-Compiler license for no apparent reason
> during compile. I am running a Verilog-only synthesis with no DesignWare
> (or other VHDL originated components.)
>
> - Romas Rudis
> Intrinsix
From: Nikolaus Mittermaier <nikolaus@synopsys.com>
John,
The reason why a VHDL-Compiler is checked out during compile are the high
level optimizations done during compile. If you start from HDL, the
license is needed for:
1. DesignWare implementation selection
2. Sharing common subexpressions
3. Resource sharing (Sharable Operators: + - * > < >= <= = /= ==)
4. Operator reordering
If you do an incremental compile on a mapped Netlist a VHDL-Compiler
license is needed to do the incremental implementation selection for
DesignWare components.
> Has Romas tried setting the Synopsys variable:
>
> hdl_prefered_license = verilog
>
> You can do a list -variables all to see what it's currently set to. I
> think the default is vhdl.
>
> - Tom Cruz
> IBM
If you set the variable "hdl_preferred_license = verilog" and no HDL-Compiler
license is available then DC will check a VHDL-Compiler license for high
level optimizations. If the variable is set to Verilog and you read a VHDL
design, a VHDL-Compiler license will be checked out.
The default value of this variable is an empty string and therefore DC
picks the first available.
- Nikolaus Mittermaier
Synopsys GmbH Munich, Germany
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