( ESNUG 378 Item 9 ) -------------------------------------------- [10/03/01]
Subject: ( ESNUG 377 #19 ) Faking Internal Clocks In Synopsys PrimeTime
> Does anyone have a way to create a clock in PrimeTime on an internal net?
>
> - Derek Brasili
> Cavium
From: Glen McDonnell <gmcdonne@ati.com>
Hi, John,
You cannot create a clock directly on a net. Since Derek doesn't appear to
want to create the clock on startpoint of the net, he should try creating
it at the endpoints of his top-level net, i.e. his hierarchical boundaries.
I'm assuming that RCLK is his top-level port and the 80 ps is the measured
wire delay from the RCLK port to the clock input of the lower-level netlist
and/or db file. Then he can use set_clock_latency to add in the 80 ps.
create_clock [get_pins {U1/ECLK U2/ECLK}] -name ECLK -period <same as RCLK>
-waveform <same as RCLK>
set_clock_latency -source 0.080 [get_clocks ECLK]
Do not set a false path between RCLK and ECLK.
- Glen McDonnell
ATI
---- ---- ---- ---- ---- ---- ----
From: [ A PrimeTime CAE ]
Hi John,
Instead of trying to run create_clock on a net, you can set create_clock
on the pin of the cell (the output pin of the driving cell or input pin
of the load cell). For example, assuming a 10 ns clock period, you would
use something similar to this:
create_clock -name ECLK -period 10 -waveform {0.08 5.08} ECLK_source_cell/Z
The key is not to run create_clock on a net but on a pin or port.
- [ A PrimeTime CAE ]
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From: "Derek Brasili" <derek.brasili@cavium.com>
Hi John,
I know you like users to follow-up once we solve a question we ask on ESNUG.
Here's the solution I found to my PrimeTime problem.
It turns out that you can define a clock on module pins. So in my case, we
have a module, lets call it GEN_ECLK. This module has an output pin called
ECLK. Now ECLK goes to a bunch of synthesized modules and is the clock to
the flops in these modules.
Now when I run PrimeTime at the top level, I am using Verilog to hook up all
the lower level modules. So my global clock, RCLK, is a port to my top
level module. So I use the following command to define ECLK as a clock and
get it to be delayed by 80 ps in reference to RCLK.
create_clock -name "rclk" -period 10 -waveform {0 5} [get_ports {rclk}]
create_generated_clock -name "eclk" -source "rclk" -edges {1 2 3}
-edge_shift {0.08 0.08 0.08} [get_pins {gen_clk/eclk}]
By doing this I have found that PrimeTime ignores the delay that it would
see from RCLK to ECLK inside of the GEN_ECLK schematic. It only uses the
80 ps delay which is what I want.
You can do a man on create_generated_clock if you don't understand what it
is doing. There is also some info on SolvNet that explains better what the
-edges and -edge_shift are doing. But if anyone has questions about it I
can explain it.
Hope this helps others facing this.
- Derek Brasili
Cavium
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