( ESNUG 375 Item 2 ) -------------------------------------------- [06/28/01]

Subject: ( ESNUG 374 #6 ) Avanti Has LEF/DEF; They Just Won't Tell You It

> Once I came to my present employer, I couldn't remember the "getClash"
> command.  I knew it existed but had lost my notes.  So I asked my AE at
> Avanti to help me out.  His response was that I had to ask the salesperson
> about anything regarding LEF/DEF.  So I asked him, and his most helpful
> response was:
> 
>    "It's good to hear from you again.  Unfortunately, we do not support
>     LEF/DEF.  We only support Verilog and GDS II.  Are you using Apollo?
>     Have you evaluated Saturn (our physical optimization)?
> 
> Yeah... I've seen Saturn in action.  Or is that "inaction"?  ...
>
> Apollo used to output DEF based upon the CEL view, not the FRAM view.  No
> clue why, but I have seen CEL views that didn't match the FRAM and the DEF
> was, well, pretty useless.  This switch changes the behavior so auDefOut
> uses FRAM for coordinate calculations:
> 
>    auSetDefOutFramBndry #t
> 
> It was probably mentioned in ESNUG before, but there it is just the same.
> 
>     - Leo Butler
>       Brocade Communications Systems, Inc.


From: [ Intel Inside ]

John,

Please keep me "anonymous" if you want to use my feedback:

Avanti does have a DEF/LEF (auDefIn/auDefOut) interface but not a complete
one.  It should work with most cases (some non-standard parsing gives extra
workaround freedom while the other needs extra scheme code to workaround).  
It's not as complete as SNPS's and Cadence's; but still working for us so
far.  And, the documentation is poor or missing for this function. 
    
I heard their new DEF/LEF API is out there already; the new one should be
better than the one I use.  They did fix some DEF/LEF input bugs for us but
may put more efforts on their new interface that I have not used yet.

I still like to use text-based design files besides any efficient binary
database so that I can always debug and workaround problems.  I wish there
were a better and more popular file format for hierarchical & timing-driven
design than today's DEF/LEF.  

    - [ Intel Inside ]
 

 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)