( ESNUG 372 Item 9 ) -------------------------------------------- [05/31/01]
Subject: ( ESNUG 371 #4 ) PhysOpt Workarounds For Bidirectional Ports
> We currently have an issue with Synopsys Physical Compiler not fixing hold
> time violations on bidirectional ports. It seems clear that PhysOpt
> understands what the violations are; we don't understand why they are not
> being fixed.
>
> - Dave Dixon
> Micron
From: [ A PhysOpt AE In The UK ]
Hi, John,
A couple of months ago I had to explain this to a customer and provide him
a workaround to the problem. I enhanced this and created a SolvNET article
which you can find with the keywords 'hold' and 'bidir'.
QUESTION:
Is there any way I can get Design Compiler (& PhysOpt) to fix hold-time
requirements on bidirectional ports?
ANSWER:
Currently Design Compiler (& PhysOpt) is incapable of fixing hold-time
requirements that are placed on a bidirectional port. The best solution to
this problem is to use separate input and output ports rather than a
bidirectional port.
At the top level, you can combine the separate signals into a combined
three-state bus.
If, however, you do not want to change the code, there might be a solution
that allows you to fix hold-time within Design Compiler (& PhysOpt).
Consider the following design, which has one cell driving the bidirectional
port. This bidirectional port has a (minimum) constraint placed on it
through set_output_delay. The driving cell is a library cell or subdesign
called BIDI.
signals in my module bidirectional cell or design port
/---------\
write_signal >>----------------| |
| BIDI |-----------<<>> bidir port
read_signal <<----------------| |
\---------/
|
direction >>--------------------/
The write_signal, read_signal, and direction commands are signals used
inside the module. To fix hold-time violations on these interface paths,
you can use a method that temporarily splits the bidirectional port by
putting this driving cell in a higher-level design. Now you can easily fix
(recalculate) the hold-time, after which you place the BIDI driving cell
back into the design.
Here are the steps.
1. First, constrain the design as usual, by using create_clock,
set_output_delay, and so on.
2. Group all cells, excluding the bidirectional drivers, in a separate
level of hierarchy, and characterize this level to get the correct
constraints:
group [get_cell -filter {@ref_name!=BIDI}] -design temp -cell itemp
characterize itemp
current_design temp
3. After you enable hold-time fixing, compile:
set_fix_hold [all_clocks]
compile -only_design_rule
4. Go back to the original design and ungroup:
current_design test
ungroup -simple itemp
This article is Methodology-224.html, the title is "Design Compiler Not
Fixing Hold-Time on Bidirectional Port" and applies to PhysOpt as well.
I hope this helps, John.
- [ A PhysOpt AE In The UK ]
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