( ESNUG 371 Item 9 ) -------------------------------------------- [05/23/01]
From: Rick Burnett <destinytech@spacey.net>
Subject: Physical Power Planing In Cadence Silicon Ensemble Sucks Big Time!
Hi, John,
I am a chip designer and I do not understand why physical power planning has
to be so difficult. I have yet to find a tool that works. The power
planner in Silicon Ensemble is total crap. The same is true to any of
Cadence's current tools. Some MINIMUM features would be:
1. Any number layer support.
2. Single metal rings to avoid via shutouts (usually rings around
blocks do this).
3. Power meshing.
4. CORRECT via creation and layer connections that are DRC clean.
Thats all I want! Right now, I have tons of perl scripts that I use to try
to automate creating a power structure and it seems like a tool like that
could save at least two weeks of work.
- Rick Burnett
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