( ESNUG 368 Item 10 ) -------------------------------------------- [04/12/01]
Subject: Finding The Geometric Center Of A Clock Tree In Cadence CTGEN
> Has anyone noticed if CTGEN has difficulty finding the geometric center in
> a segment of logic? This might be influenced by the placement of the root
> pin for the clock. Dealing with a segment of logic (FIR FILTER), but the
> entry point of the root pin is in lower right corner. (internal clock).
>
> From the 'human' view it seems like the tool should have any easy time
> with this, but I am seeing over 0.9 ns of skew. What is even more
> puzzling is that I have given CTGEN a large max delay (according to manual
> this gives CTGEN plenty of margin to play with...) But, no solution.
> There is a larger TAP and the tool seems to do fine with getting good
> skew. But the larger TAP is spread out and the entry point for the root
> pin is near the center of the rectangular topology of that logic....
>
> There is something quirky about this algorithm which makes the tool take a
> dive and it is not clear what the paramters might be which cause the bug
> to get cornered. Any folks who might have some insights on the
> personality of the CTGEN tool, (5.2 or 5.3), please introduce me....
>
> - Jim O'Keefe
From: Ralf Leisner <leisner@cadence.com>
Usually there is a reason why CTGen could not fulfill your requirements. In
CTGen's working directory you would find a sub-dir 'rpt' and there is a file
'final.analysis' containing the slowest and fastest path for every clocktree
generated (min path, max path). You would find there detailed informations
about cell delays, interconnect delays, loads and transition times at every
stage of every clocktree. Look for significant differences between the min
path and max path of the concerning clock. In conjunction with the
graphical view of your design's floorplan/clocktree it is possible to
find out the reason for the irregularity in most of cases.
- Ralf Leisner
Cadence Design Systems GmbH Haar, Germany
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