( ESNUG 366 Item 9 ) --------------------------------------------- [02/23/01]
From: "Gregg Lahti" <gregg.d.lahti@intel.com>
Subject: Undocumented DC Varible For VHDL'87 & VHDL'93 Incompatibilities
Hi, John,
Somewhere between 1998.08 and 2000.05, DC changed its method of reading
VHDL. I got bit by this when I was pulling in some legacy VHDL code that
synthesized fine in 1998.08 that used the following constaint declaration:
constant nc1 : std_logic_vector(3 downto 0) := to_stdlogicvector(X"01");
In 2000.05, DC would error reading in the VHDL on the line above with an
"expression is ambiguous" message. Turns out, that DC 2000.05 and higher
revs by default read in VHDL '93. An undocumented variable "hdlin_vhdl_87"
is required to be set to true for the above code to work:
set hdlin_vhdl_87 true ;# Tcl mode, '87 compatible read
or
hdlin_vhdl_87 = true # DCSH mode
Initially, Synopsys Support offered up the '93 compatible code workaround.
To be 2000.05 & VHDL '93 compatible, the X"01" needs type coersion to a
bit_vector type. The following code works if you're in the default '93
mode in 2000.05:
constant nc1 :
std_logic_vector(3 downto 0) := to_stdlogicvector(bit_vector'(X"01"));
Note that the hdlin_vhdl_87 doesn't exist. A "info vars hdlin*" or the
standard help commands didn't show it. Nowhere in SOLVNET or the DC docs
was this documented and it took about a month to get this resolved by
Synopsys support after I complained that it worked fine in prev versions
(so much for reuse, right?). Of course, by the second day of this problem
I wound up converting all 200+ of my constant declarations into a hard
std_logic_vector value to get my synth job done. :^(
Somewhere, Cliff Cummings is laughing at the hoops we VHDL users go
through...
- Gregg Lahti
Intel Corp
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