( ESNUG 361 Item 8 ) --------------------------------------------- [11/16/00]
Subject: ( ESNUG 360 #13 ) A User Compares Synopsys SystemC vs. CynLib
> Our group has been evaluating SystemC and CynApps and we plan to embrace
> one of them. For that, it is very important to get a comparison chart
> between these two tools/languages which are built around the same concept.
>
> Can anybody point me to some website or give me some pointers regarding
> why one is better than the other? I am looking at criteria like:
>
> * licensing mode
> * generation of waveforms
> * which is more popular and more used in industry and universities
> * which has more 3rd party vendor and tool support
> * simplicity of use, resemblance to Verilog
> * do we have Verilog "to" and "from" translators
> * most important, how is the PLI interface architected and how it works
>
> Thank you for your help.
>
> - Satyajit Chowdhury
> Cisco Systems San Jose, CA
From: [ No Names, Please ]
Hi John,
Attached is a text file which is my compiled report comparing SystemC and
CynApps. You can publish this is you remove all instances of any employee
name and of my company's name.
- [ No Names, Please ]
1. Licensing mode.
~~~~~~~~~~~~~~~~~~
SystemC: The license, which is free of any charges, allows access to the
source code for SystemC class libraries and the reference
simulation kernel. This is pretty unrestricted for internal use
in your organization. There is a commercial use attachment if
you wish to re-sell/re-distibute the code outside your company.
There have been some issues you may have heard about in the media
concerning the license. These issues were mainly of concern to
EDA vendors and resolving those issues (basically by ensuring
key decisions were in the hands of the steering group rather than
any one company) was key to getting Cadence to come on board
June 2000.
Something that has all the advantages of Open Source, but also
gives EDA/IP companies better ability to offer proprietary
value-added innovation on top of SystemC.
CynApps: Essentially the same as the Mozilla Public License, which is
listed as a "Free License" according to the GNU project. See
http://www.gnu.org/philosophy/license-list.html for details.
2. Reliability : open bugs, customer complaints.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: None I know of. Probably people submit the fixes if they find
any and that is rolled out in the next version. For example,
right now, a discussion is going on in the forum regarding the
format in which SystemC generates VCD files being incompatible
with Verilog generation.
CynApps: No known problems.
3. Learning curve - time spent to come up to speed with the tool.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: With basic C and C++ knowledge in addition to HW knowledge, it
takes about a week of reading before starting to write code.
CynApps: Free version has roughly the same learning curve as SystemC.
Cynapps offers Cyn++, which allows one to write Verilog-like
Cyn++ code which is converted into C++.
4. Number of associated partners, companies backing the tool.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: The direction and control of SystemC is now shared between all
SystemC users and the thirteen companies who form the Steering
Group. These companies are: ARM, Cadence, CoWare, Ericsson,
Fujitsu, Infineon, Lucent, Motorola, NEC, Sony, Synopsys, TI,
and STMicroelectronics.
CynApps: Cadence, Chronology, and TransModeling have all announced
Cynlib-based tools.
5. Documentation, "help"/"man" feature, user-friendliness.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: The manual is well-written and it is updated with every revision.
They are supposed to release an LRM late 2000.
CynApps: Documentation gives good description of how Cynlib works, but has
not been updated for the latest version (documentation is rev
1.1, latest Cynlib version 1.2). A separate LRM describes the
Cynlib language.
6. Technical support, freq of user newsgroup & mailing lists letters.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: SystemC has a open messageboard for the user community to share
ideas and support. It's the only C++ hardware language that has
one. Traffic in the mailing list is considerable. About 5-6
mails a day.
CynApps: Cynapps has given very good pre-sales support, and I believe
they would continue to give good support, however they are still
a single-product company. Traffic on mailing list near-zero.
7. University interest and projects.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Academic interest in SystemC is very strong. At least 20
universities doing research projects using SystemC. Two are UC
Irvine (Prof. Rajesh Gupta) and U. Tuebingen (Prof. Rosenstiel)
CynApps: Cynapps has announced a program to provide Cynlib to
universities, along with training, but did not name any
universities participating.
8. White papers, articles, general interest from industry, demos.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: 3 new companies joined the steering group in June 2000: Cadence,
Motorola and NEC. SystemC user groups in China, Japan, Sweden.
SystemC training and demos from Synopsys, Willamette HDL.
CynApps: Press releases for three companies listed above.
9. 3rd party vendors, debugging facilities.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Last DAC (in June) 16 companies in the areas of EDA, IP and
Training announced SystemC support for over 20 products.
CynApps: Partnerships announced with Chronology, Cadence, and
TransModeling.
10. Closeness to Verilog, simplicity of use.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Code structure is very similar to Verilog although syntax
is different.
CynApps: Code structure is very similar to Verilog although syntax
is different.
11. Ease of cosimulation with Verilog, plain C - PLI architecture.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Several APIs have been developed for different situations:
- Fast transaction oriented IF for emulation - IKOS
- VCS PLI/Scirocco/MTI cosimulation with SystemC - Synopsys
- Multi-simulator cosimulation - Transmodeling
- Multi-simulator SystemC model generation tools - TBA
CynApps: Cynlib PLI interface is an add-on product, using a simple
function-call for each signal to be connected. Also have
home-grown PLI interface for no additional $$$, works with VCS.
12. Platform support ( Windows, Linux, Solaris )
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Runs in all three.
CynApps: Runs in Solaris and Linux, probably not in Windows.
13. Simulation time, swap memory usage, handling of big designs.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Yet to do any performance measurement.
CynApps: Performance appears to be equivalent to Verilog at same level of
detail. No scalability measures, although RTP may be able to
give input into large designs and scalability.
14. Translators to and from Verilog code.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Several are available including capabilities within Synopsys
CoCentric SystemC Compiler, Frontier Design's AR/T Designer as
part of the synthesis capabilities. Also available is Tension
Technologies VTOC for going from Verilog to C/SystemC.
CynApps: Verilog to CynLib translators available.
CynLib to Verilog translator in development.
15. Waveform generation and related flexibility.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Generates VCD files. Supported by VeriTools, TransModeling,
Blue Pacific, VirSim, Innoveda, plus other commercial packages.
Our current version of virsim 4.0.1 cannot open a dump file
generated by SystemC simulator. But SignalScan can open it.
The reason is virsim expects a VCD+ format file ( or VPD file )
whereas SystemC generates VCD file.
CynApps: Cynlib presently generates VCD files, support for other binary
formats promised. Support for VPD unlikely since virsim is
owned by Synopsys.
For both tools, virsim can open a VCD file if you run vcd2vpd on it first.
16. Roadmap for the tool.
~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Define a C++ class library and simulation kernel for:
* HW modeling: clocks, concurrency, process, signal, datatypes
* SW modeling: interrupts
* systems modeling: abstract communication.
Time frame : July 2000 (validated v1.1 with SystemC v1.1 LRM)
Late 2000 (v1.2 with hierarchical links and
communication refinement)
2001 (v2.0+ with performance models and
RTOS integration)
Even later (v3.x analog/mixed signal support)
CynApps: Simulation language is essentially complete. Further plans are
for commercial tool releases for the Cynlib language.
Verilog-to-C translation tool has been released and used by RTP.
C-to-Verilog "synthesis" tool is in production.
17. Popularity - number of software downloads.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: Total downloads of SystemC stands at over 14,000 for all versions
and this is from over 5,500 registered licensees from over 500
companies from Oct 99 through Aug 2000. Alignment with VSIA SLD
Datatypes.
CynApps: Downloads do not translate well to number of actual users, and
CynApps does not track number of downloads.
18. Range of abstraction.
~~~~~~~~~~~~~~~~~~~~~~~~~
SystemC: A language that offers a lot more abstration than basic HDLs.
- Abstract Communications Protocols - you can model blocks
talking to one another, without specifying each and every
signal / connection, then easily refine the protocol and
method of communication.
- Arbitrary width datatypes - not locked to just 32, 64 bit
boundaries.
- Fixed point datatypes - very important for DSP applications
- supports 4 state logic in v1.1 (0,1,x,z)
CynApps: Cynapps presently supports 2 levels of logic, and support for
3 levels of logic has been promised in the next release (0, 1,
and Z). Also all of the above except 4 state logic.
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