( ESNUG 361 Item 3 ) --------------------------------------------- [11/16/00]
Subject: ( ESNUG 360 #12 ) Ambit-RTL & Interra Concorde *Loves* Aggregates
> I have a piece of VHDL that represents a problem with the Synopsys DC
> parser and aggregates...
>
> architecture arch1 of top is
>
> signal temp_1, temp_2 : std_logic_vector (1 downto 0);
>
> begin
>
> temp_1 <= (1 downto 0 => a_bit_1);
> temp_2 <= (1 downto 0 => a_bit_2);
>
> output_1 <= (a_vector_1 and temp_1) or
> (a_vector_2 and temp_2);
> output_2 <= (a_vector_1 and (1 downto 0 => a_bit_1)) or
> (a_vector_2 and (1 downto 0 => a_bit_2));
> end arch1;
>
> Both output_1 and output_2 should be equivalent, but they're not! Design
> Compiler and Tuxedo both have problems reading in output_2.
>
> - Mike Dotson
> IBM
From: Ravikumar Surepeddi <rkumar@interra.com>
Hi, John,
Synopsys DC 2000.05 doesn't support VHDL aggregates usage as pointed by Mike
for output_2.
dc_shell trace:
--------------
elaborate top
Error: Can't determine type of aggregate or concat
in routine top line 26 in file '/interra/test/vhdl/aggtest.vhdl'
(HDL-123)
No designs were read
0
current_design top
A brief note on myself: I work for company Interra Inc. (www.interra.com).
Interra has a fast RTL synthesis tool by name Concorde. Concorde can be
used as front-end to formal verification tool or design synthesis tool.
Concorde does support Mike's requirement. The Concorde netlist is given
below for your reference. Concorde netlist:
a_vector_1_INT <= (a_vector_1);
a_vector_2_INT <= (a_vector_2);
a_bit_1_INT <= (a_bit_1);
a_bit_2_INT <= (a_bit_2);
output_1 <= (output_1_INT);
output_2 <= (output_2_INT);
rtlc_I7 : INT_AND2
Port Map (Z=>rtlc_N11(0),in1=>a_vector_1_IN(0),in2=>a_bit_1_INT);
rtlc_I8 : INT_AND2
Port Map (Z=>rtlc_N11(1),in1=>a_vector_1_IN(1),in2=>a_bit_1_INT);
rtlc_I11 : INT_AND2
Port Map (Z=>rtlc_N16(0),in1=>a_vector_2_IN(0),in2=>a_bit_2_INT);
rtlc_I12 : INT_AND2
Port Map (Z=>rtlc_N16(1),in1=>a_vector_2_IN(1),in2=>a_bit_2_INT);
rtlc_I15 : INT_OR2
Port Map (Z=>output_1_INT(0),in1=>rtlc_N11(0),in2=>rtlc_N16(0));
rtlc_I16 : INT_OR2
Port Map (Z=>output_1_INT(1),in1=>rtlc_N11(1),in2=>rtlc_N16(1));
rtlc_I35 : INT_BUF
Port Map (Z=>output_2_INT(1),A=>output_1_INT(1));
rtlc_I36 : INT_BUF
Port Map (Z=>output_2_INT(0),A=>output_1_INT(0));
Please note the netlist representation is with Interra's generic library
here. INT_AND2 corresponds to the VHDL logical operator "and", INT_OR2
corresponds to the VHDL logical operator "or" etc. Also, Please note that
Concorde takes care of parallel output instances correctly. temp_1 and
temp_2 optmized away. The synthesis tool has a -preserve option to preserve
intermediate signals if needed.
- Ravikumar Surepeddi
Interra Inc. San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Paul Graham <pgraham@cadence.com>
John,
Regarding the Design Compiler VHDL Aggregates Parser problem, I'm sure
you'll be happy to know that Ambit BuildGates handles this little test case
just fine. It parses the test case and generates correct logic both in the
current version (v4.0) and in the oldest version I could access (v2.3.12,
from September 1999).
This item caught my eye since I wrote the Ambit VHDL parser. :-)
- Paul Graham
Cadence
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